simple_thread.hh (12109:f29e9c5418aa) | simple_thread.hh (12406:86bde4a026b5) |
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1/* 2 * Copyright (c) 2011-2012, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 32 unchanged lines hidden (view full) --- 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 */ 44 45#ifndef __CPU_SIMPLE_THREAD_HH__ 46#define __CPU_SIMPLE_THREAD_HH__ 47 48#include "arch/decoder.hh" | 1/* 2 * Copyright (c) 2011-2012, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 32 unchanged lines hidden (view full) --- 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 */ 44 45#ifndef __CPU_SIMPLE_THREAD_HH__ 46#define __CPU_SIMPLE_THREAD_HH__ 47 48#include "arch/decoder.hh" |
49#include "arch/generic/tlb.hh" |
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49#include "arch/isa.hh" 50#include "arch/isa_traits.hh" 51#include "arch/registers.hh" | 50#include "arch/isa.hh" 51#include "arch/isa_traits.hh" 52#include "arch/registers.hh" |
52#include "arch/tlb.hh" | |
53#include "arch/types.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh" 58#include "debug/CCRegs.hh" 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" --- 69 unchanged lines hidden (view full) --- 130 { 131 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 132 } 133 134 ProxyThreadContext<SimpleThread> *tc; 135 136 System *system; 137 | 53#include "arch/types.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh" 58#include "debug/CCRegs.hh" 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" --- 69 unchanged lines hidden (view full) --- 130 { 131 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 132 } 133 134 ProxyThreadContext<SimpleThread> *tc; 135 136 System *system; 137 |
138 TheISA::TLB *itb; 139 TheISA::TLB *dtb; | 138 BaseTLB *itb; 139 BaseTLB *dtb; |
140 141 TheISA::Decoder decoder; 142 143 // constructor: initialize SimpleThread from given process structure 144 // FS 145 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, | 140 141 TheISA::Decoder decoder; 142 143 // constructor: initialize SimpleThread from given process structure 144 // FS 145 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, |
146 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa, | 146 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, |
147 bool use_kernel_stats = true); 148 // SE 149 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, | 147 bool use_kernel_stats = true); 148 // SE 149 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, |
150 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb, | 150 Process *_process, BaseTLB *_itb, BaseTLB *_dtb, |
151 TheISA::ISA *_isa); 152 153 virtual ~SimpleThread(); 154 155 virtual void takeOverFrom(ThreadContext *oldContext); 156 157 void regStats(const std::string &name); 158 --- 37 unchanged lines hidden (view full) --- 196 bool simPalCheck(int palFunc); 197 198 /******************************************* 199 * ThreadContext interface functions. 200 ******************************************/ 201 202 BaseCPU *getCpuPtr() { return baseCpu; } 203 | 151 TheISA::ISA *_isa); 152 153 virtual ~SimpleThread(); 154 155 virtual void takeOverFrom(ThreadContext *oldContext); 156 157 void regStats(const std::string &name); 158 --- 37 unchanged lines hidden (view full) --- 196 bool simPalCheck(int palFunc); 197 198 /******************************************* 199 * ThreadContext interface functions. 200 ******************************************/ 201 202 BaseCPU *getCpuPtr() { return baseCpu; } 203 |
204 TheISA::TLB *getITBPtr() { return itb; } | 204 BaseTLB *getITBPtr() { return itb; } |
205 | 205 |
206 TheISA::TLB *getDTBPtr() { return dtb; } | 206 BaseTLB *getDTBPtr() { return dtb; } |
207 208 CheckerCPU *getCheckerCpuPtr() { return NULL; } 209 210 TheISA::Decoder *getDecoderPtr() { return &decoder; } 211 212 System *getSystemPtr() { return system; } 213 214 Status status() const { return _status; } --- 386 unchanged lines hidden --- | 207 208 CheckerCPU *getCheckerCpuPtr() { return NULL; } 209 210 TheISA::Decoder *getDecoderPtr() { return &decoder; } 211 212 System *getSystemPtr() { return system; } 213 214 Status status() const { return _status; } --- 386 unchanged lines hidden --- |