simple_thread.hh (10934:5af8f40d8f2c) simple_thread.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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53#include "arch/types.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/thread_context.hh"
57#include "cpu/thread_state.hh"
58#include "debug/CCRegs.hh"
59#include "debug/FloatRegs.hh"
60#include "debug/IntRegs.hh"
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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53#include "arch/types.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/thread_context.hh"
57#include "cpu/thread_state.hh"
58#include "debug/CCRegs.hh"
59#include "debug/FloatRegs.hh"
60#include "debug/IntRegs.hh"
61#include "debug/VectorRegs.hh"
62#include "mem/page_table.hh"
63#include "mem/request.hh"
64#include "sim/byteswap.hh"
65#include "sim/eventq.hh"
66#include "sim/process.hh"
67#include "sim/serialize.hh"
68#include "sim/system.hh"
69

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98class SimpleThread : public ThreadState
99{
100 protected:
101 typedef TheISA::MachInst MachInst;
102 typedef TheISA::MiscReg MiscReg;
103 typedef TheISA::FloatReg FloatReg;
104 typedef TheISA::FloatRegBits FloatRegBits;
105 typedef TheISA::CCReg CCReg;
61#include "mem/page_table.hh"
62#include "mem/request.hh"
63#include "sim/byteswap.hh"
64#include "sim/eventq.hh"
65#include "sim/process.hh"
66#include "sim/serialize.hh"
67#include "sim/system.hh"
68

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97class SimpleThread : public ThreadState
98{
99 protected:
100 typedef TheISA::MachInst MachInst;
101 typedef TheISA::MiscReg MiscReg;
102 typedef TheISA::FloatReg FloatReg;
103 typedef TheISA::FloatRegBits FloatRegBits;
104 typedef TheISA::CCReg CCReg;
106 typedef TheISA::VectorReg VectorReg;
107
108 public:
109 typedef ThreadContext::Status Status;
110
111 protected:
112 union {
113 FloatReg f[TheISA::NumFloatRegs];
114 FloatRegBits i[TheISA::NumFloatRegs];
115 } floatRegs;
116 TheISA::IntReg intRegs[TheISA::NumIntRegs];
105 public:
106 typedef ThreadContext::Status Status;
107
108 protected:
109 union {
110 FloatReg f[TheISA::NumFloatRegs];
111 FloatRegBits i[TheISA::NumFloatRegs];
112 } floatRegs;
113 TheISA::IntReg intRegs[TheISA::NumIntRegs];
117
118#ifdef ISA_HAS_CC_REGS
119 TheISA::CCReg ccRegs[TheISA::NumCCRegs];
120#endif
114#ifdef ISA_HAS_CC_REGS
115 TheISA::CCReg ccRegs[TheISA::NumCCRegs];
116#endif
121
122#ifdef ISA_HAS_VECTOR_REGS
123 TheISA::VectorReg vectorRegs[TheISA::NumVectorRegs];
124#endif
125
126 TheISA::ISA *const isa; // one "instance" of the current ISA.
127
128 TheISA::PCState _pcState;
129
130 /** Did this instruction execute or is it predicated false */
131 bool predicate;
132
133 public:

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286 reg_idx, flatIndex, regVal);
287 return regVal;
288#else
289 panic("Tried to read a CC register.");
290 return 0;
291#endif
292 }
293
117 TheISA::ISA *const isa; // one "instance" of the current ISA.
118
119 TheISA::PCState _pcState;
120
121 /** Did this instruction execute or is it predicated false */
122 bool predicate;
123
124 public:

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277 reg_idx, flatIndex, regVal);
278 return regVal;
279#else
280 panic("Tried to read a CC register.");
281 return 0;
282#endif
283 }
284
294 const VectorReg &readVectorReg(int reg_idx)
295 {
296 int flatIndex = isa->flattenVectorIndex(reg_idx);
297 assert(0 <= flatIndex);
298 assert(flatIndex < TheISA::NumVectorRegs);
299 DPRINTF(VectorRegs, "Reading vector reg %d (%d).\n",
300 reg_idx, flatIndex);
301 return readVectorRegFlat(flatIndex);
302 }
303
304 void setIntReg(int reg_idx, uint64_t val)
305 {
306 int flatIndex = isa->flattenIntIndex(reg_idx);
307 assert(flatIndex < TheISA::NumIntRegs);
308 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
309 reg_idx, flatIndex, val);
310 setIntRegFlat(flatIndex, val);
311 }

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339 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
340 reg_idx, flatIndex, val);
341 setCCRegFlat(flatIndex, val);
342#else
343 panic("Tried to set a CC register.");
344#endif
345 }
346
285 void setIntReg(int reg_idx, uint64_t val)
286 {
287 int flatIndex = isa->flattenIntIndex(reg_idx);
288 assert(flatIndex < TheISA::NumIntRegs);
289 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
290 reg_idx, flatIndex, val);
291 setIntRegFlat(flatIndex, val);
292 }

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320 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
321 reg_idx, flatIndex, val);
322 setCCRegFlat(flatIndex, val);
323#else
324 panic("Tried to set a CC register.");
325#endif
326 }
327
347 void setVectorReg(int reg_idx, const VectorReg &val)
348 {
349#ifdef ISA_HAS_VECTOR_REGS
350 int flatIndex = isa->flattenVectorIndex(reg_idx);
351 assert(flatIndex < TheISA::NumVectorRegs);
352 DPRINTF(VectorRegs, "Setting vector reg %d (%d).\n",
353 reg_idx, flatIndex);
354 setVectorRegFlat(flatIndex, val);
355#else
356 panic("Tried to set a vector register.");
357#endif
358 }
359
360 TheISA::PCState
361 pcState()
362 {
363 return _pcState;
364 }
365
366 void
367 pcState(const TheISA::PCState &val)

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441
442 int
443 flattenCCIndex(int reg)
444 {
445 return isa->flattenCCIndex(reg);
446 }
447
448 int
328 TheISA::PCState
329 pcState()
330 {
331 return _pcState;
332 }
333
334 void
335 pcState(const TheISA::PCState &val)

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409
410 int
411 flattenCCIndex(int reg)
412 {
413 return isa->flattenCCIndex(reg);
414 }
415
416 int
449 flattenVectorIndex(int reg)
450 {
451 return isa->flattenVectorIndex(reg);
452 }
453
454 int
455 flattenMiscIndex(int reg)
456 {
457 return isa->flattenMiscIndex(reg);
458 }
459
460 unsigned readStCondFailures() { return storeCondFailures; }
461
462 void setStCondFailures(unsigned sc_failures)

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483 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
484#else
485 CCReg readCCRegFlat(int idx)
486 { panic("readCCRegFlat w/no CC regs!\n"); }
487
488 void setCCRegFlat(int idx, CCReg val)
489 { panic("setCCRegFlat w/no CC regs!\n"); }
490#endif
417 flattenMiscIndex(int reg)
418 {
419 return isa->flattenMiscIndex(reg);
420 }
421
422 unsigned readStCondFailures() { return storeCondFailures; }
423
424 void setStCondFailures(unsigned sc_failures)

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445 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
446#else
447 CCReg readCCRegFlat(int idx)
448 { panic("readCCRegFlat w/no CC regs!\n"); }
449
450 void setCCRegFlat(int idx, CCReg val)
451 { panic("setCCRegFlat w/no CC regs!\n"); }
452#endif
491
492#ifdef ISA_HAS_VECTOR_REGS
493 const VectorReg &readVectorRegFlat(int idx) { return vectorRegs[idx]; }
494 void setVectorRegFlat(int idx, const VectorReg &val)
495 { vectorRegs[idx] = val; }
496#else
497 const VectorReg &readVectorRegFlat(int idx)
498 { panic("readVectorRegFlat w/no Vector regs!\n"); }
499
500 void setVectorRegFlat(int idx, const VectorReg &val)
501 { panic("setVectorRegFlat w/no Vector regs!\n"); }
502#endif
503};
504
505
506#endif // __CPU_CPU_EXEC_CONTEXT_HH__
453};
454
455
456#endif // __CPU_CPU_EXEC_CONTEXT_HH__