1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2001-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 */
44
45#ifndef __CPU_SIMPLE_THREAD_HH__
46#define __CPU_SIMPLE_THREAD_HH__
47
48#include "arch/decoder.hh"
49#include "arch/generic/tlb.hh"
50#include "arch/isa.hh"
51#include "arch/isa_traits.hh"
52#include "arch/registers.hh"
53#include "arch/types.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/thread_context.hh"
57#include "cpu/thread_state.hh"
58#include "debug/CCRegs.hh"
59#include "debug/FloatRegs.hh"
60#include "debug/IntRegs.hh"
61#include "debug/VecPredRegs.hh"
62#include "debug/VecRegs.hh"
63#include "mem/page_table.hh"
64#include "mem/request.hh"
65#include "sim/byteswap.hh"
66#include "sim/eventq.hh"
67#include "sim/process.hh"
68#include "sim/serialize.hh"
69#include "sim/system.hh"
70
71class BaseCPU;
72class CheckerCPU;
73
74class FunctionProfile;
75class ProfileNode;
76
77namespace Kernel {
78 class Statistics;
79}
80
81/**
82 * The SimpleThread object provides a combination of the ThreadState
83 * object and the ThreadContext interface. It implements the
84 * ThreadContext interface and adds to the ThreadState object by adding all
85 * the objects needed for simple functional execution, including a
86 * simple architectural register file, and pointers to the ITB and DTB
87 * in full system mode. For CPU models that do not need more advanced
88 * ways to hold state (i.e. a separate physical register file, or
89 * separate fetch and commit PC's), this SimpleThread class provides
90 * all the necessary state for full architecture-level functional
91 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
92 * examples.
93 */
94
95class SimpleThread : public ThreadState, public ThreadContext
96{
97 protected:
98 typedef TheISA::MachInst MachInst;
99 using VecRegContainer = TheISA::VecRegContainer;
100 using VecElem = TheISA::VecElem;
101 using VecPredRegContainer = TheISA::VecPredRegContainer;
102 public:
103 typedef ThreadContext::Status Status;
104
105 protected:
106 RegVal floatRegs[TheISA::NumFloatRegs];
107 RegVal intRegs[TheISA::NumIntRegs];
108 VecRegContainer vecRegs[TheISA::NumVecRegs];
109 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
110#ifdef ISA_HAS_CC_REGS
111 RegVal ccRegs[TheISA::NumCCRegs];
112#endif
113 TheISA::ISA *const isa; // one "instance" of the current ISA.
114
115 TheISA::PCState _pcState;
116
117 /** Did this instruction execute or is it predicated false */
118 bool predicate;
119
120 /** True if the memory access should be skipped for this instruction */
121 bool memAccPredicate;
122
123 public:
124 std::string name() const
125 {
126 return csprintf("%s.[tid:%i]", baseCpu->name(), threadId());
127 }
128
129 System *system;
130
131 BaseTLB *itb;
132 BaseTLB *dtb;
133
134 TheISA::Decoder decoder;
135
136 // constructor: initialize SimpleThread from given process structure
137 // FS
138 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
139 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa,
140 bool use_kernel_stats = true);
141 // SE
142 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
143 Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
144 TheISA::ISA *_isa);
145
146 virtual ~SimpleThread() {}
147
148 void takeOverFrom(ThreadContext *oldContext) override;
149
150 void regStats(const std::string &name) override;
151
152 void copyState(ThreadContext *oldContext);
153
154 void serialize(CheckpointOut &cp) const override;
155 void unserialize(CheckpointIn &cp) override;
156 void startup();
157
158 /***************************************************************
159 * SimpleThread functions to provide CPU with access to various
160 * state.
161 **************************************************************/
162
163 /** Returns the pointer to this SimpleThread's ThreadContext. Used
164 * when a ThreadContext must be passed to objects outside of the
165 * CPU.
166 */
167 ThreadContext *getTC() { return this; }
168
169 void demapPage(Addr vaddr, uint64_t asn)
170 {
171 itb->demapPage(vaddr, asn);
172 dtb->demapPage(vaddr, asn);
173 }
174
175 void demapInstPage(Addr vaddr, uint64_t asn)
176 {
177 itb->demapPage(vaddr, asn);
178 }
179
180 void demapDataPage(Addr vaddr, uint64_t asn)
181 {
182 dtb->demapPage(vaddr, asn);
183 }
184
185 void dumpFuncProfile() override;
186
187 /*******************************************
188 * ThreadContext interface functions.
189 ******************************************/
190
191 BaseCPU *getCpuPtr() override { return baseCpu; }
192
193 int cpuId() const override { return ThreadState::cpuId(); }
194 uint32_t socketId() const override { return ThreadState::socketId(); }
195 int threadId() const override { return ThreadState::threadId(); }
196 void setThreadId(int id) override { ThreadState::setThreadId(id); }
197 ContextID contextId() const override { return ThreadState::contextId(); }
198 void setContextId(ContextID id) override { ThreadState::setContextId(id); }
199
200 BaseTLB *getITBPtr() override { return itb; }
201
202 BaseTLB *getDTBPtr() override { return dtb; }
203
204 CheckerCPU *getCheckerCpuPtr() override { return NULL; }
205
206 TheISA::ISA *getIsaPtr() override { return isa; }
207
208 TheISA::Decoder *getDecoderPtr() override { return &decoder; }
209
210 System *getSystemPtr() override { return system; }
211
212 Kernel::Statistics *
213 getKernelStats() override
214 {
215 return ThreadState::getKernelStats();
216 }
217
218 PortProxy &getPhysProxy() override { return ThreadState::getPhysProxy(); }
|
227 getMemProxy() override
228 {
229 return ThreadState::getMemProxy();
230 }
231
232 Process *getProcessPtr() override { return ThreadState::getProcessPtr(); }
233 void setProcessPtr(Process *p) override { ThreadState::setProcessPtr(p); }
234
235 Status status() const override { return _status; }
236
237 void setStatus(Status newStatus) override { _status = newStatus; }
238
239 /// Set the status to Active.
240 void activate() override;
241
242 /// Set the status to Suspended.
243 void suspend() override;
244
245 /// Set the status to Halted.
246 void halt() override;
247
248 EndQuiesceEvent *
249 getQuiesceEvent() override
250 {
251 return ThreadState::getQuiesceEvent();
252 }
253
254 Tick
255 readLastActivate() override
256 {
257 return ThreadState::readLastActivate();
258 }
259 Tick
260 readLastSuspend() override
261 {
262 return ThreadState::readLastSuspend();
263 }
264
265 void profileClear() override { ThreadState::profileClear(); }
266 void profileSample() override { ThreadState::profileSample(); }
267
268 void copyArchRegs(ThreadContext *tc) override;
269
270 void clearArchRegs() override
271 {
272 _pcState = 0;
273 memset(intRegs, 0, sizeof(intRegs));
274 memset(floatRegs, 0, sizeof(floatRegs));
275 for (int i = 0; i < TheISA::NumVecRegs; i++) {
276 vecRegs[i].zero();
277 }
278 for (int i = 0; i < TheISA::NumVecPredRegs; i++) {
279 vecPredRegs[i].reset();
280 }
281#ifdef ISA_HAS_CC_REGS
282 memset(ccRegs, 0, sizeof(ccRegs));
283#endif
284 isa->clear();
285 }
286
287 //
288 // New accessors for new decoder.
289 //
290 RegVal
291 readIntReg(RegIndex reg_idx) const override
292 {
293 int flatIndex = isa->flattenIntIndex(reg_idx);
294 assert(flatIndex < TheISA::NumIntRegs);
295 uint64_t regVal(readIntRegFlat(flatIndex));
296 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
297 reg_idx, flatIndex, regVal);
298 return regVal;
299 }
300
301 RegVal
302 readFloatReg(RegIndex reg_idx) const override
303 {
304 int flatIndex = isa->flattenFloatIndex(reg_idx);
305 assert(flatIndex < TheISA::NumFloatRegs);
306 RegVal regVal(readFloatRegFlat(flatIndex));
307 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
308 reg_idx, flatIndex, regVal);
309 return regVal;
310 }
311
312 const VecRegContainer&
313 readVecReg(const RegId& reg) const override
314 {
315 int flatIndex = isa->flattenVecIndex(reg.index());
316 assert(flatIndex < TheISA::NumVecRegs);
317 const VecRegContainer& regVal = readVecRegFlat(flatIndex);
318 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
319 reg.index(), flatIndex, regVal.print());
320 return regVal;
321 }
322
323 VecRegContainer&
324 getWritableVecReg(const RegId& reg) override
325 {
326 int flatIndex = isa->flattenVecIndex(reg.index());
327 assert(flatIndex < TheISA::NumVecRegs);
328 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
329 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
330 reg.index(), flatIndex, regVal.print());
331 return regVal;
332 }
333
334 /** Vector Register Lane Interfaces. */
335 /** @{ */
336 /** Reads source vector <T> operand. */
337 template <typename T>
338 VecLaneT<T, true>
339 readVecLane(const RegId& reg) const
340 {
341 int flatIndex = isa->flattenVecIndex(reg.index());
342 assert(flatIndex < TheISA::NumVecRegs);
343 auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex());
344 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n",
345 reg.index(), flatIndex, reg.elemIndex(), regVal);
346 return regVal;
347 }
348
349 /** Reads source vector 8bit operand. */
350 virtual ConstVecLane8
351 readVec8BitLaneReg(const RegId ®) const override
352 {
353 return readVecLane<uint8_t>(reg);
354 }
355
356 /** Reads source vector 16bit operand. */
357 virtual ConstVecLane16
358 readVec16BitLaneReg(const RegId ®) const override
359 {
360 return readVecLane<uint16_t>(reg);
361 }
362
363 /** Reads source vector 32bit operand. */
364 virtual ConstVecLane32
365 readVec32BitLaneReg(const RegId ®) const override
366 {
367 return readVecLane<uint32_t>(reg);
368 }
369
370 /** Reads source vector 64bit operand. */
371 virtual ConstVecLane64
372 readVec64BitLaneReg(const RegId ®) const override
373 {
374 return readVecLane<uint64_t>(reg);
375 }
376
377 /** Write a lane of the destination vector register. */
378 template <typename LD>
379 void
380 setVecLaneT(const RegId ®, const LD &val)
381 {
382 int flatIndex = isa->flattenVecIndex(reg.index());
383 assert(flatIndex < TheISA::NumVecRegs);
384 setVecLaneFlat(flatIndex, reg.elemIndex(), val);
385 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n",
386 reg.index(), flatIndex, reg.elemIndex(), val);
387 }
388 virtual void
389 setVecLane(const RegId ®, const LaneData<LaneSize::Byte> &val) override
390 {
391 return setVecLaneT(reg, val);
392 }
393 virtual void
394 setVecLane(const RegId ®,
395 const LaneData<LaneSize::TwoByte> &val) override
396 {
397 return setVecLaneT(reg, val);
398 }
399 virtual void
400 setVecLane(const RegId ®,
401 const LaneData<LaneSize::FourByte> &val) override
402 {
403 return setVecLaneT(reg, val);
404 }
405 virtual void
406 setVecLane(const RegId ®,
407 const LaneData<LaneSize::EightByte> &val) override
408 {
409 return setVecLaneT(reg, val);
410 }
411 /** @} */
412
413 const VecElem &
414 readVecElem(const RegId ®) const override
415 {
416 int flatIndex = isa->flattenVecElemIndex(reg.index());
417 assert(flatIndex < TheISA::NumVecRegs);
418 const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex());
419 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
420 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
421 return regVal;
422 }
423
424 const VecPredRegContainer &
425 readVecPredReg(const RegId ®) const override
426 {
427 int flatIndex = isa->flattenVecPredIndex(reg.index());
428 assert(flatIndex < TheISA::NumVecPredRegs);
429 const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex);
430 DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
431 reg.index(), flatIndex, regVal.print());
432 return regVal;
433 }
434
435 VecPredRegContainer &
436 getWritableVecPredReg(const RegId ®) override
437 {
438 int flatIndex = isa->flattenVecPredIndex(reg.index());
439 assert(flatIndex < TheISA::NumVecPredRegs);
440 VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex);
441 DPRINTF(VecPredRegs,
442 "Reading predicate reg %d (%d) as %s for modify.\n",
443 reg.index(), flatIndex, regVal.print());
444 return regVal;
445 }
446
447 RegVal
448 readCCReg(RegIndex reg_idx) const override
449 {
450#ifdef ISA_HAS_CC_REGS
451 int flatIndex = isa->flattenCCIndex(reg_idx);
452 assert(0 <= flatIndex);
453 assert(flatIndex < TheISA::NumCCRegs);
454 uint64_t regVal(readCCRegFlat(flatIndex));
455 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
456 reg_idx, flatIndex, regVal);
457 return regVal;
458#else
459 panic("Tried to read a CC register.");
460 return 0;
461#endif
462 }
463
464 void
465 setIntReg(RegIndex reg_idx, RegVal val) override
466 {
467 int flatIndex = isa->flattenIntIndex(reg_idx);
468 assert(flatIndex < TheISA::NumIntRegs);
469 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
470 reg_idx, flatIndex, val);
471 setIntRegFlat(flatIndex, val);
472 }
473
474 void
475 setFloatReg(RegIndex reg_idx, RegVal val) override
476 {
477 int flatIndex = isa->flattenFloatIndex(reg_idx);
478 assert(flatIndex < TheISA::NumFloatRegs);
479 // XXX: Fix array out of bounds compiler error for gem5.fast
480 // when checkercpu enabled
481 if (flatIndex < TheISA::NumFloatRegs)
482 setFloatRegFlat(flatIndex, val);
483 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n",
484 reg_idx, flatIndex, val);
485 }
486
487 void
488 setVecReg(const RegId ®, const VecRegContainer &val) override
489 {
490 int flatIndex = isa->flattenVecIndex(reg.index());
491 assert(flatIndex < TheISA::NumVecRegs);
492 setVecRegFlat(flatIndex, val);
493 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n",
494 reg.index(), flatIndex, val.print());
495 }
496
497 void
498 setVecElem(const RegId ®, const VecElem &val) override
499 {
500 int flatIndex = isa->flattenVecElemIndex(reg.index());
501 assert(flatIndex < TheISA::NumVecRegs);
502 setVecElemFlat(flatIndex, reg.elemIndex(), val);
503 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to"
504 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
505 }
506
507 void
508 setVecPredReg(const RegId ®, const VecPredRegContainer &val) override
509 {
510 int flatIndex = isa->flattenVecPredIndex(reg.index());
511 assert(flatIndex < TheISA::NumVecPredRegs);
512 setVecPredRegFlat(flatIndex, val);
513 DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
514 reg.index(), flatIndex, val.print());
515 }
516
517 void
518 setCCReg(RegIndex reg_idx, RegVal val) override
519 {
520#ifdef ISA_HAS_CC_REGS
521 int flatIndex = isa->flattenCCIndex(reg_idx);
522 assert(flatIndex < TheISA::NumCCRegs);
523 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
524 reg_idx, flatIndex, val);
525 setCCRegFlat(flatIndex, val);
526#else
527 panic("Tried to set a CC register.");
528#endif
529 }
530
531 TheISA::PCState pcState() const override { return _pcState; }
532 void pcState(const TheISA::PCState &val) override { _pcState = val; }
533
534 void
535 pcStateNoRecord(const TheISA::PCState &val) override
536 {
537 _pcState = val;
538 }
539
540 Addr instAddr() const override { return _pcState.instAddr(); }
541 Addr nextInstAddr() const override { return _pcState.nextInstAddr(); }
542 MicroPC microPC() const override { return _pcState.microPC(); }
543 bool readPredicate() const { return predicate; }
544 void setPredicate(bool val) { predicate = val; }
545
546 RegVal
547 readMiscRegNoEffect(RegIndex misc_reg) const override
548 {
549 return isa->readMiscRegNoEffect(misc_reg);
550 }
551
552 RegVal
553 readMiscReg(RegIndex misc_reg) override
554 {
555 return isa->readMiscReg(misc_reg, this);
556 }
557
558 void
559 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
560 {
561 return isa->setMiscRegNoEffect(misc_reg, val);
562 }
563
564 void
565 setMiscReg(RegIndex misc_reg, RegVal val) override
566 {
567 return isa->setMiscReg(misc_reg, val, this);
568 }
569
570 RegId
571 flattenRegId(const RegId& regId) const override
572 {
573 return isa->flattenRegId(regId);
574 }
575
576 unsigned readStCondFailures() const override { return storeCondFailures; }
577
578 bool
579 readMemAccPredicate()
580 {
581 return memAccPredicate;
582 }
583
584 void
585 setMemAccPredicate(bool val)
586 {
587 memAccPredicate = val;
588 }
589
590 void
591 setStCondFailures(unsigned sc_failures) override
592 {
593 storeCondFailures = sc_failures;
594 }
595
596 Counter
597 readFuncExeInst() const override
598 {
599 return ThreadState::readFuncExeInst();
600 }
601
602 void
603 syscall(int64_t callnum, Fault *fault) override
604 {
605 process->syscall(callnum, this, fault);
606 }
607
608 RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; }
609 void
610 setIntRegFlat(RegIndex idx, RegVal val) override
611 {
612 intRegs[idx] = val;
613 }
614
615 RegVal
616 readFloatRegFlat(RegIndex idx) const override
617 {
618 return floatRegs[idx];
619 }
620 void
621 setFloatRegFlat(RegIndex idx, RegVal val) override
622 {
623 floatRegs[idx] = val;
624 }
625
626 const VecRegContainer &
627 readVecRegFlat(RegIndex reg) const override
628 {
629 return vecRegs[reg];
630 }
631
632 VecRegContainer &
633 getWritableVecRegFlat(RegIndex reg) override
634 {
635 return vecRegs[reg];
636 }
637
638 void
639 setVecRegFlat(RegIndex reg, const VecRegContainer &val) override
640 {
641 vecRegs[reg] = val;
642 }
643
644 template <typename T>
645 VecLaneT<T, true>
646 readVecLaneFlat(RegIndex reg, int lId) const
647 {
648 return vecRegs[reg].laneView<T>(lId);
649 }
650
651 template <typename LD>
652 void
653 setVecLaneFlat(RegIndex reg, int lId, const LD &val)
654 {
655 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
656 }
657
658 const VecElem &
659 readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
660 {
661 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
662 }
663
664 void
665 setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
666 const VecElem &val) override
667 {
668 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
669 }
670
671 const VecPredRegContainer &
672 readVecPredRegFlat(RegIndex reg) const override
673 {
674 return vecPredRegs[reg];
675 }
676
677 VecPredRegContainer &
678 getWritableVecPredRegFlat(RegIndex reg) override
679 {
680 return vecPredRegs[reg];
681 }
682
683 void
684 setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override
685 {
686 vecPredRegs[reg] = val;
687 }
688
689#ifdef ISA_HAS_CC_REGS
690 RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
691 void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; }
692#else
693 RegVal
694 readCCRegFlat(RegIndex idx) const override
695 {
696 panic("readCCRegFlat w/no CC regs!\n");
697 }
698
699 void
700 setCCRegFlat(RegIndex idx, RegVal val) override
701 {
702 panic("setCCRegFlat w/no CC regs!\n");
703 }
704#endif
705};
706
707
708#endif // __CPU_CPU_EXEC_CONTEXT_HH__
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