1/* 2 * Copyright (c) 2011 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. |
4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated --- 38 unchanged lines hidden (view full) --- 50#include "arch/isa_traits.hh" 51#include "arch/registers.hh" 52#include "arch/tlb.hh" 53#include "arch/types.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh" |
58#include "debug/CCRegs.hh" |
59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" 61#include "mem/page_table.hh" 62#include "mem/request.hh" 63#include "sim/byteswap.hh" 64#include "sim/eventq.hh" 65#include "sim/process.hh" 66#include "sim/serialize.hh" --- 29 unchanged lines hidden (view full) --- 96 97class SimpleThread : public ThreadState 98{ 99 protected: 100 typedef TheISA::MachInst MachInst; 101 typedef TheISA::MiscReg MiscReg; 102 typedef TheISA::FloatReg FloatReg; 103 typedef TheISA::FloatRegBits FloatRegBits; |
104 typedef TheISA::CCReg CCReg; |
105 public: 106 typedef ThreadContext::Status Status; 107 108 protected: 109 union { 110 FloatReg f[TheISA::NumFloatRegs]; 111 FloatRegBits i[TheISA::NumFloatRegs]; 112 } floatRegs; 113 TheISA::IntReg intRegs[TheISA::NumIntRegs]; |
114#ifdef ISA_HAS_CC_REGS 115 TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 116#endif |
117 TheISA::ISA *const isa; // one "instance" of the current ISA. 118 119 TheISA::PCState _pcState; 120 121 /** Did this instruction execute or is it predicated false */ 122 bool predicate; 123 124 public: --- 100 unchanged lines hidden (view full) --- 225 226 void copyArchRegs(ThreadContext *tc); 227 228 void clearArchRegs() 229 { 230 _pcState = 0; 231 memset(intRegs, 0, sizeof(intRegs)); 232 memset(floatRegs.i, 0, sizeof(floatRegs.i)); |
233#ifdef ISA_HAS_CC_REGS 234 memset(ccRegs, 0, sizeof(ccRegs)); 235#endif |
236 isa->clear(); 237 } 238 239 // 240 // New accessors for new decoder. 241 // 242 uint64_t readIntReg(int reg_idx) 243 { --- 20 unchanged lines hidden (view full) --- 264 int flatIndex = isa->flattenFloatIndex(reg_idx); 265 assert(flatIndex < TheISA::NumFloatRegs); 266 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 267 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 268 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 269 return regVal; 270 } 271 |
272 CCReg readCCReg(int reg_idx) 273 { 274#ifdef ISA_HAS_CC_REGS 275 int flatIndex = isa->flattenCCIndex(reg_idx); 276 assert(flatIndex < TheISA::NumCCRegs); 277 uint64_t regVal(readCCRegFlat(flatIndex)); 278 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 279 reg_idx, flatIndex, regVal); 280 return regVal; 281#else 282 panic("Tried to read a CC register."); 283 return 0; 284#endif 285 } 286 |
287 void setIntReg(int reg_idx, uint64_t val) 288 { 289 int flatIndex = isa->flattenIntIndex(reg_idx); 290 assert(flatIndex < TheISA::NumIntRegs); 291 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 292 reg_idx, flatIndex, val); 293 setIntRegFlat(flatIndex, val); 294 } --- 14 unchanged lines hidden (view full) --- 309 // XXX: Fix array out of bounds compiler error for gem5.fast 310 // when checkercpu enabled 311 if (flatIndex < TheISA::NumFloatRegs) 312 setFloatRegBitsFlat(flatIndex, val); 313 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 314 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 315 } 316 |
317 void setCCReg(int reg_idx, CCReg val) 318 { 319#ifdef ISA_HAS_CC_REGS 320 int flatIndex = isa->flattenCCIndex(reg_idx); 321 assert(flatIndex < TheISA::NumCCRegs); 322 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 323 reg_idx, flatIndex, val); 324 setCCRegFlat(flatIndex, val); 325#else 326 panic("Tried to set a CC register."); 327#endif 328 } 329 |
330 TheISA::PCState 331 pcState() 332 { 333 return _pcState; 334 } 335 336 void 337 pcState(const TheISA::PCState &val) --- 66 unchanged lines hidden (view full) --- 404 } 405 406 int 407 flattenFloatIndex(int reg) 408 { 409 return isa->flattenFloatIndex(reg); 410 } 411 |
412 int 413 flattenCCIndex(int reg) 414 { 415 return isa->flattenCCIndex(reg); 416 } 417 |
418 unsigned readStCondFailures() { return storeCondFailures; } 419 420 void setStCondFailures(unsigned sc_failures) 421 { storeCondFailures = sc_failures; } 422 423 void syscall(int64_t callnum) 424 { 425 process->syscall(callnum, tc); --- 5 unchanged lines hidden (view full) --- 431 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 432 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 433 434 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 435 void setFloatRegBitsFlat(int idx, FloatRegBits val) { 436 floatRegs.i[idx] = val; 437 } 438 |
439#ifdef ISA_HAS_CC_REGS 440 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 441 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 442#else 443 CCReg readCCRegFlat(int idx) 444 { panic("readCCRegFlat w/no CC regs!\n"); } 445 446 void setCCRegFlat(int idx, CCReg val) 447 { panic("setCCRegFlat w/no CC regs!\n"); } 448#endif |
449}; 450 451 452// for non-speculative execution context, spec_mode is always false 453inline bool 454SimpleThread::misspeculating() 455{ 456 return false; 457} 458 459#endif // __CPU_CPU_EXEC_CONTEXT_HH__ |