1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 371 unchanged lines hidden (view full) --- 380 381 void setStCondFailures(unsigned sc_failures) 382 { storeCondFailures = sc_failures; } 383 384#if !FULL_SYSTEM 385 TheISA::IntReg getSyscallArg(int i) 386 { 387 assert(i < TheISA::NumArgumentRegs); |
388 TheISA::IntReg val = regs.readIntReg( 389 TheISA::flattenIntIndex(getTC(), TheISA::ArgumentReg[i])); 390#if THE_ISA == SPARC_ISA 391 if (bits(this->readMiscRegNoEffect( 392 SparcISA::MISCREG_PSTATE), 3, 3)) { 393 val = bits(val, 31, 0); 394 } 395#endif 396 return val; |
397 } 398 399 // used to shift args for indirect syscall 400 void setSyscallArg(int i, TheISA::IntReg val) 401 { 402 assert(i < TheISA::NumArgumentRegs); 403 regs.setIntReg(TheISA::flattenIntIndex(getTC(), 404 TheISA::ArgumentReg[i]), val); --- 23 unchanged lines hidden --- |