1/* 2 * Copyright (c) 2011-2012, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 85 unchanged lines hidden (view full) --- 94 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 95 * examples. 96 */ 97 98class SimpleThread : public ThreadState 99{ 100 protected: 101 typedef TheISA::MachInst MachInst; |
102 typedef TheISA::CCReg CCReg; 103 using VecRegContainer = TheISA::VecRegContainer; 104 using VecElem = TheISA::VecElem; 105 public: 106 typedef ThreadContext::Status Status; 107 108 protected: |
109 RegVal floatRegs[TheISA::NumFloatRegs]; 110 RegVal intRegs[TheISA::NumIntRegs]; |
111 VecRegContainer vecRegs[TheISA::NumVecRegs]; 112#ifdef ISA_HAS_CC_REGS 113 TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 114#endif 115 TheISA::ISA *const isa; // one "instance" of the current ISA. 116 117 TheISA::PCState _pcState; 118 --- 113 unchanged lines hidden (view full) --- 232 memset(ccRegs, 0, sizeof(ccRegs)); 233#endif 234 isa->clear(); 235 } 236 237 // 238 // New accessors for new decoder. 239 // |
240 RegVal 241 readIntReg(int reg_idx) |
242 { 243 int flatIndex = isa->flattenIntIndex(reg_idx); 244 assert(flatIndex < TheISA::NumIntRegs); 245 uint64_t regVal(readIntRegFlat(flatIndex)); 246 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 247 reg_idx, flatIndex, regVal); 248 return regVal; 249 } 250 |
251 RegVal 252 readFloatRegBits(int reg_idx) |
253 { 254 int flatIndex = isa->flattenFloatIndex(reg_idx); 255 assert(flatIndex < TheISA::NumFloatRegs); |
256 RegVal regVal(readFloatRegBitsFlat(flatIndex)); |
257 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 258 reg_idx, flatIndex, regVal); 259 return regVal; 260 } 261 262 const VecRegContainer& 263 readVecReg(const RegId& reg) const 264 { --- 97 unchanged lines hidden (view full) --- 362 reg_idx, flatIndex, regVal); 363 return regVal; 364#else 365 panic("Tried to read a CC register."); 366 return 0; 367#endif 368 } 369 |
370 void 371 setIntReg(int reg_idx, RegVal val) |
372 { 373 int flatIndex = isa->flattenIntIndex(reg_idx); 374 assert(flatIndex < TheISA::NumIntRegs); 375 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 376 reg_idx, flatIndex, val); 377 setIntRegFlat(flatIndex, val); 378 } 379 |
380 void 381 setFloatRegBits(int reg_idx, RegVal val) |
382 { 383 int flatIndex = isa->flattenFloatIndex(reg_idx); 384 assert(flatIndex < TheISA::NumFloatRegs); 385 // XXX: Fix array out of bounds compiler error for gem5.fast 386 // when checkercpu enabled 387 if (flatIndex < TheISA::NumFloatRegs) 388 setFloatRegBitsFlat(flatIndex, val); 389 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 390 reg_idx, flatIndex, val); 391 } 392 |
393 void 394 setVecReg(const RegId& reg, const VecRegContainer& val) |
395 { 396 int flatIndex = isa->flattenVecIndex(reg.index()); 397 assert(flatIndex < TheISA::NumVecRegs); 398 setVecRegFlat(flatIndex, val); 399 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 400 reg.index(), flatIndex, val.print()); 401 } 402 |
403 void 404 setVecElem(const RegId& reg, const VecElem& val) |
405 { 406 int flatIndex = isa->flattenVecElemIndex(reg.index()); 407 assert(flatIndex < TheISA::NumVecRegs); 408 setVecElemFlat(flatIndex, reg.elemIndex(), val); 409 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 410 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 411 } 412 |
413 void 414 setCCReg(int reg_idx, CCReg val) |
415 { 416#ifdef ISA_HAS_CC_REGS 417 int flatIndex = isa->flattenCCIndex(reg_idx); 418 assert(flatIndex < TheISA::NumCCRegs); 419 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 420 reg_idx, flatIndex, val); 421 setCCRegFlat(flatIndex, val); 422#else --- 48 unchanged lines hidden (view full) --- 471 return predicate; 472 } 473 474 void setPredicate(bool val) 475 { 476 predicate = val; 477 } 478 |
479 RegVal 480 readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const |
481 { 482 return isa->readMiscRegNoEffect(misc_reg); 483 } 484 |
485 RegVal 486 readMiscReg(int misc_reg, ThreadID tid=0) |
487 { 488 return isa->readMiscReg(misc_reg, tc); 489 } 490 491 void |
492 setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0) |
493 { 494 return isa->setMiscRegNoEffect(misc_reg, val); 495 } 496 497 void |
498 setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0) |
499 { 500 return isa->setMiscReg(misc_reg, val, tc); 501 } 502 503 RegId 504 flattenRegId(const RegId& regId) const 505 { 506 return isa->flattenRegId(regId); 507 } 508 509 unsigned readStCondFailures() { return storeCondFailures; } 510 511 void setStCondFailures(unsigned sc_failures) 512 { storeCondFailures = sc_failures; } 513 |
514 void 515 syscall(int64_t callnum, Fault *fault) |
516 { 517 process->syscall(callnum, tc, fault); 518 } 519 |
520 RegVal readIntRegFlat(int idx) { return intRegs[idx]; } 521 void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } |
522 |
523 RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } 524 void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; } |
525 |
526 const VecRegContainer & 527 readVecRegFlat(const RegIndex& reg) const |
528 { 529 return vecRegs[reg]; 530 } 531 |
532 VecRegContainer & 533 getWritableVecRegFlat(const RegIndex& reg) |
534 { 535 return vecRegs[reg]; 536 } 537 |
538 void 539 setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) |
540 { 541 vecRegs[reg] = val; 542 } 543 544 template <typename T> |
545 VecLaneT 546 readVecLaneFlat(const RegIndex& reg, int lId) const |
547 { 548 return vecRegs[reg].laneView<T>(lId); 549 } 550 551 template <typename LD> |
552 void 553 setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) |
554 { 555 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 556 } 557 |
558 const VecElem & 559 readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const |
560 { 561 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 562 } 563 |
564 void 565 setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 566 const VecElem val) |
567 { 568 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 569 } 570 571#ifdef ISA_HAS_CC_REGS 572 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 573 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 574#else 575 CCReg readCCRegFlat(int idx) 576 { panic("readCCRegFlat w/no CC regs!\n"); } 577 578 void setCCRegFlat(int idx, CCReg val) 579 { panic("setCCRegFlat w/no CC regs!\n"); } 580#endif 581}; 582 583 584#endif // __CPU_CPU_EXEC_CONTEXT_HH__ |