102,104d101
< typedef TheISA::MiscReg MiscReg;
< typedef TheISA::FloatReg FloatReg;
< typedef TheISA::FloatRegBits FloatRegBits;
112,113c109,110
< FloatRegBits floatRegs[TheISA::NumFloatRegs];
< TheISA::IntReg intRegs[TheISA::NumIntRegs];
---
> RegVal floatRegs[TheISA::NumFloatRegs];
> RegVal intRegs[TheISA::NumIntRegs];
243c240,241
< uint64_t readIntReg(int reg_idx)
---
> RegVal
> readIntReg(int reg_idx)
253c251,252
< FloatRegBits readFloatRegBits(int reg_idx)
---
> RegVal
> readFloatRegBits(int reg_idx)
257c256
< FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
---
> RegVal regVal(readFloatRegBitsFlat(flatIndex));
371c370,371
< void setIntReg(int reg_idx, uint64_t val)
---
> void
> setIntReg(int reg_idx, RegVal val)
380c380,381
< void setFloatRegBits(int reg_idx, FloatRegBits val)
---
> void
> setFloatRegBits(int reg_idx, RegVal val)
392c393,394
< void setVecReg(const RegId& reg, const VecRegContainer& val)
---
> void
> setVecReg(const RegId& reg, const VecRegContainer& val)
401c403,404
< void setVecElem(const RegId& reg, const VecElem& val)
---
> void
> setVecElem(const RegId& reg, const VecElem& val)
410c413,414
< void setCCReg(int reg_idx, CCReg val)
---
> void
> setCCReg(int reg_idx, CCReg val)
475,476c479,480
< MiscReg
< readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
---
> RegVal
> readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
481,482c485,486
< MiscReg
< readMiscReg(int misc_reg, ThreadID tid = 0)
---
> RegVal
> readMiscReg(int misc_reg, ThreadID tid=0)
488c492
< setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
---
> setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0)
494c498
< setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
---
> setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0)
510c514,515
< void syscall(int64_t callnum, Fault *fault)
---
> void
> syscall(int64_t callnum, Fault *fault)
515,516c520,521
< uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
< void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
---
> RegVal readIntRegFlat(int idx) { return intRegs[idx]; }
> void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; }
518,521c523,524
< FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs[idx]; }
< void setFloatRegBitsFlat(int idx, FloatRegBits val) {
< floatRegs[idx] = val;
< }
---
> RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; }
> void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; }
523c526,527
< const VecRegContainer& readVecRegFlat(const RegIndex& reg) const
---
> const VecRegContainer &
> readVecRegFlat(const RegIndex& reg) const
528c532,533
< VecRegContainer& getWritableVecRegFlat(const RegIndex& reg)
---
> VecRegContainer &
> getWritableVecRegFlat(const RegIndex& reg)
533c538,539
< void setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
---
> void
> setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
539c545,546
< VecLaneT<T, true> readVecLaneFlat(const RegIndex& reg, int lId) const
---
> VecLaneT<T, true>
> readVecLaneFlat(const RegIndex& reg, int lId) const
545c552,553
< void setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
---
> void
> setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
550,551c558,559
< const VecElem& readVecElemFlat(const RegIndex& reg,
< const ElemIndex& elemIndex) const
---
> const VecElem &
> readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const
556,557c564,566
< void setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
< const VecElem val)
---
> void
> setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
> const VecElem val)