235,303d234
< /*
< template <class T>
< Fault read(RequestPtr &req, T &data)
< {
< #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
< if (req->isLocked()) {
< req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
< req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
< }
< #endif
<
< Fault error;
< error = mem->prot_read(req->paddr, data, req->size);
< data = LittleEndianGuest::gtoh(data);
< return error;
< }
<
< template <class T>
< Fault write(RequestPtr &req, T &data)
< {
< #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
< ExecContext *xc;
<
< // If this is a store conditional, act appropriately
< if (req->isLocked()) {
< xc = req->xc;
<
< if (req->isUncacheable()) {
< // Don't update result register (see stq_c in isa_desc)
< req->result = 2;
< xc->setStCondFailures(0);//Needed? [RGD]
< } else {
< bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
< Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
< req->result = lock_flag;
< if (!lock_flag ||
< ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
< xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
< xc->setStCondFailures(xc->readStCondFailures() + 1);
< if (((xc->readStCondFailures()) % 100000) == 0) {
< std::cerr << "Warning: "
< << xc->readStCondFailures()
< << " consecutive store conditional failures "
< << "on cpu " << req->xc->readCpuId()
< << std::endl;
< }
< return NoFault;
< }
< else xc->setStCondFailures(0);
< }
< }
<
< // Need to clear any locked flags on other proccessors for
< // this address. Only do this for succsful Store Conditionals
< // and all other stores (WH64?). Unsuccessful Store
< // Conditionals would have returned above, and wouldn't fall
< // through.
< for (int i = 0; i < system->execContexts.size(); i++){
< xc = system->execContexts[i];
< if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
< (req->paddr & ~0xf)) {
< xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
< }
< }
<
< #endif
< return mem->prot_write(req->paddr, (T)htog(data), req->size);
< }
< */