86,88c86
< * ThreadContext interface so that a ProxyThreadContext class can be
< * made using SimpleThread as the template parameter (see
< * thread_context.hh). It adds to the ThreadState object by adding all
---
> * ThreadContext interface and adds to the ThreadState object by adding all
99c97
< class SimpleThread : public ThreadState
---
> class SimpleThread : public ThreadState, public ThreadContext
127c125
< return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
---
> return csprintf("%s.[tid:%i]", baseCpu->name(), threadId());
130,131d127
< ProxyThreadContext<SimpleThread> *tc;
<
149c145
< virtual ~SimpleThread();
---
> virtual ~SimpleThread() {}
151c147
< virtual void takeOverFrom(ThreadContext *oldContext);
---
> void takeOverFrom(ThreadContext *oldContext) override;
153c149
< void regStats(const std::string &name);
---
> void regStats(const std::string &name) override;
170c166
< ThreadContext *getTC() { return tc; }
---
> ThreadContext *getTC() { return this; }
188c184
< void dumpFuncProfile();
---
> void dumpFuncProfile() override;
198c194
< BaseCPU *getCpuPtr() { return baseCpu; }
---
> BaseCPU *getCpuPtr() override { return baseCpu; }
200c196,201
< BaseTLB *getITBPtr() { return itb; }
---
> int cpuId() const override { return ThreadState::cpuId(); }
> uint32_t socketId() const override { return ThreadState::socketId(); }
> int threadId() const override { return ThreadState::threadId(); }
> void setThreadId(int id) override { ThreadState::setThreadId(id); }
> ContextID contextId() const override { return ThreadState::contextId(); }
> void setContextId(ContextID id) override { ThreadState::setContextId(id); }
202c203
< BaseTLB *getDTBPtr() { return dtb; }
---
> BaseTLB *getITBPtr() override { return itb; }
204c205
< CheckerCPU *getCheckerCpuPtr() { return NULL; }
---
> BaseTLB *getDTBPtr() override { return dtb; }
206c207
< TheISA::ISA *getIsaPtr() { return isa; }
---
> CheckerCPU *getCheckerCpuPtr() override { return NULL; }
208c209
< TheISA::Decoder *getDecoderPtr() { return &decoder; }
---
> TheISA::ISA *getIsaPtr() override { return isa; }
210c211
< System *getSystemPtr() { return system; }
---
> TheISA::Decoder *getDecoderPtr() override { return &decoder; }
212c213
< Status status() const { return _status; }
---
> System *getSystemPtr() override { return system; }
214c215,219
< void setStatus(Status newStatus) { _status = newStatus; }
---
> TheISA::Kernel::Statistics *
> getKernelStats()
> {
> return ThreadState::getKernelStats();
> }
215a221,241
> PortProxy &getPhysProxy() { return ThreadState::getPhysProxy(); }
> FSTranslatingPortProxy &
> getVirtProxy()
> {
> return ThreadState::getVirtProxy();
> }
>
> void initMemProxies(ThreadContext *tc) { ThreadState::initMemProxies(tc); }
> SETranslatingPortProxy &
> getMemProxy()
> {
> return ThreadState::getMemProxy();
> }
>
> Process *getProcessPtr() { return ThreadState::getProcessPtr(); }
> void setProcessPtr(Process *p) override { ThreadState::setProcessPtr(p); }
>
> Status status() const override { return _status; }
>
> void setStatus(Status newStatus) override { _status = newStatus; }
>
217c243
< void activate();
---
> void activate() override;
220c246
< void suspend();
---
> void suspend() override;
223c249
< void halt();
---
> void halt() override;
225c251,255
< void copyArchRegs(ThreadContext *tc);
---
> EndQuiesceEvent *
> getQuiesceEvent() override
> {
> return ThreadState::getQuiesceEvent();
> }
227c257,258
< void clearArchRegs()
---
> Tick
> readLastActivate() override
228a260,274
> return ThreadState::readLastActivate();
> }
> Tick
> readLastSuspend() override
> {
> return ThreadState::readLastSuspend();
> }
>
> void profileClear() override { ThreadState::profileClear(); }
> void profileSample() override { ThreadState::profileSample(); }
>
> void copyArchRegs(ThreadContext *tc) override;
>
> void clearArchRegs() override
> {
248c294
< readIntReg(int reg_idx)
---
> readIntReg(RegIndex reg_idx) const override
259c305
< readFloatReg(int reg_idx)
---
> readFloatReg(RegIndex reg_idx) const override
270c316
< readVecReg(const RegId& reg) const
---
> readVecReg(const RegId& reg) const override
281c327
< getWritableVecReg(const RegId& reg)
---
> getWritableVecReg(const RegId& reg) override
308,309c354,357
< readVec8BitLaneReg(const RegId& reg) const
< { return readVecLane<uint8_t>(reg); }
---
> readVec8BitLaneReg(const RegId ®) const override
> {
> return readVecLane<uint8_t>(reg);
> }
313,314c361,364
< readVec16BitLaneReg(const RegId& reg) const
< { return readVecLane<uint16_t>(reg); }
---
> readVec16BitLaneReg(const RegId ®) const override
> {
> return readVecLane<uint16_t>(reg);
> }
318,319c368,371
< readVec32BitLaneReg(const RegId& reg) const
< { return readVecLane<uint32_t>(reg); }
---
> readVec32BitLaneReg(const RegId ®) const override
> {
> return readVecLane<uint32_t>(reg);
> }
323,324c375,378
< readVec64BitLaneReg(const RegId& reg) const
< { return readVecLane<uint64_t>(reg); }
---
> readVec64BitLaneReg(const RegId ®) const override
> {
> return readVecLane<uint64_t>(reg);
> }
328c382,383
< void setVecLaneT(const RegId& reg, const LD& val)
---
> void
> setVecLaneT(const RegId ®, const LD &val)
336,347c391,413
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::Byte>& val)
< { return setVecLaneT(reg, val); }
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::TwoByte>& val)
< { return setVecLaneT(reg, val); }
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::FourByte>& val)
< { return setVecLaneT(reg, val); }
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::EightByte>& val)
< { return setVecLaneT(reg, val); }
---
> virtual void
> setVecLane(const RegId ®, const LaneData<LaneSize::Byte> &val) override
> {
> return setVecLaneT(reg, val);
> }
> virtual void
> setVecLane(const RegId ®,
> const LaneData<LaneSize::TwoByte> &val) override
> {
> return setVecLaneT(reg, val);
> }
> virtual void
> setVecLane(const RegId ®,
> const LaneData<LaneSize::FourByte> &val) override
> {
> return setVecLaneT(reg, val);
> }
> virtual void
> setVecLane(const RegId ®,
> const LaneData<LaneSize::EightByte> &val) override
> {
> return setVecLaneT(reg, val);
> }
350c416,417
< const VecElem& readVecElem(const RegId& reg) const
---
> const VecElem &
> readVecElem(const RegId ®) const override
360,361c427,428
< const VecPredRegContainer&
< readVecPredReg(const RegId& reg) const
---
> const VecPredRegContainer &
> readVecPredReg(const RegId ®) const override
371,372c438,439
< VecPredRegContainer&
< getWritableVecPredReg(const RegId& reg)
---
> VecPredRegContainer &
> getWritableVecPredReg(const RegId ®) override
384c451
< readCCReg(int reg_idx)
---
> readCCReg(RegIndex reg_idx) const override
401c468
< setIntReg(int reg_idx, RegVal val)
---
> setIntReg(RegIndex reg_idx, RegVal val) override
411c478
< setFloatReg(int reg_idx, RegVal val)
---
> setFloatReg(RegIndex reg_idx, RegVal val) override
424c491
< setVecReg(const RegId& reg, const VecRegContainer& val)
---
> setVecReg(const RegId ®, const VecRegContainer &val) override
434c501
< setVecElem(const RegId& reg, const VecElem& val)
---
> setVecElem(const RegId ®, const VecElem &val) override
444c511
< setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
---
> setVecPredReg(const RegId ®, const VecPredRegContainer &val) override
454c521
< setCCReg(int reg_idx, RegVal val)
---
> setCCReg(RegIndex reg_idx, RegVal val) override
467,471c534,535
< TheISA::PCState
< pcState()
< {
< return _pcState;
< }
---
> TheISA::PCState pcState() const override { return _pcState; }
> void pcState(const TheISA::PCState &val) override { _pcState = val; }
474c538
< pcState(const TheISA::PCState &val)
---
> pcStateNoRecord(const TheISA::PCState &val) override
479,483c543,547
< void
< pcStateNoRecord(const TheISA::PCState &val)
< {
< _pcState = val;
< }
---
> Addr instAddr() const override { return _pcState.instAddr(); }
> Addr nextInstAddr() const override { return _pcState.nextInstAddr(); }
> MicroPC microPC() const override { return _pcState.microPC(); }
> bool readPredicate() const { return predicate; }
> void setPredicate(bool val) { predicate = val; }
485,486c549,550
< Addr
< instAddr()
---
> RegVal
> readMiscRegNoEffect(RegIndex misc_reg) const override
488c552
< return _pcState.instAddr();
---
> return isa->readMiscRegNoEffect(misc_reg);
491,492c555,556
< Addr
< nextInstAddr()
---
> RegVal
> readMiscReg(RegIndex misc_reg) override
494c558
< return _pcState.nextInstAddr();
---
> return isa->readMiscReg(misc_reg, this);
498c562
< setNPC(Addr val)
---
> setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
500c564
< _pcState.setNPC(val);
---
> return isa->setMiscRegNoEffect(misc_reg, val);
503,504c567,568
< MicroPC
< microPC()
---
> void
> setMiscReg(RegIndex misc_reg, RegVal val) override
506c570
< return _pcState.microPC();
---
> return isa->setMiscReg(misc_reg, val, this);
509c573,574
< bool readPredicate()
---
> RegId
> flattenRegId(const RegId& regId) const override
511c576
< return predicate;
---
> return isa->flattenRegId(regId);
514,517c579
< void setPredicate(bool val)
< {
< predicate = val;
< }
---
> unsigned readStCondFailures() const override { return storeCondFailures; }
519,520c581,582
< RegVal
< readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
---
> void
> setStCondFailures(unsigned sc_failures) override
522c584
< return isa->readMiscRegNoEffect(misc_reg);
---
> storeCondFailures = sc_failures;
525,526c587,588
< RegVal
< readMiscReg(int misc_reg, ThreadID tid=0)
---
> Counter
> readFuncExeInst() const override
528c590
< return isa->readMiscReg(misc_reg, tc);
---
> return ThreadState::readFuncExeInst();
532c594
< setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0)
---
> syscall(int64_t callnum, Fault *fault) override
534c596
< return isa->setMiscRegNoEffect(misc_reg, val);
---
> process->syscall(callnum, this, fault);
536a599
> RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; }
538c601
< setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0)
---
> setIntRegFlat(RegIndex idx, RegVal val) override
540c603
< return isa->setMiscReg(misc_reg, val, tc);
---
> intRegs[idx] = val;
543,544c606,607
< RegId
< flattenRegId(const RegId& regId) const
---
> RegVal
> readFloatRegFlat(RegIndex idx) const override
546c609
< return isa->flattenRegId(regId);
---
> return floatRegs[idx];
548,553d610
<
< unsigned readStCondFailures() { return storeCondFailures; }
<
< void setStCondFailures(unsigned sc_failures)
< { storeCondFailures = sc_failures; }
<
555c612
< syscall(int64_t callnum, Fault *fault)
---
> setFloatRegFlat(RegIndex idx, RegVal val) override
557c614
< process->syscall(callnum, tc, fault);
---
> floatRegs[idx] = val;
560,565d616
< RegVal readIntRegFlat(int idx) { return intRegs[idx]; }
< void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; }
<
< RegVal readFloatRegFlat(int idx) { return floatRegs[idx]; }
< void setFloatRegFlat(int idx, RegVal val) { floatRegs[idx] = val; }
<
567c618
< readVecRegFlat(const RegIndex& reg) const
---
> readVecRegFlat(RegIndex reg) const override
573c624
< getWritableVecRegFlat(const RegIndex& reg)
---
> getWritableVecRegFlat(RegIndex reg) override
579c630
< setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
---
> setVecRegFlat(RegIndex reg, const VecRegContainer &val) override
586c637
< readVecLaneFlat(const RegIndex& reg, int lId) const
---
> readVecLaneFlat(RegIndex reg, int lId) const
593c644
< setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
---
> setVecLaneFlat(RegIndex reg, int lId, const LD &val)
599c650
< readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const
---
> readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
605,606c656,657
< setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
< const VecElem val)
---
> setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
> const VecElem &val) override
611c662,663
< const VecPredRegContainer& readVecPredRegFlat(const RegIndex& reg) const
---
> const VecPredRegContainer &
> readVecPredRegFlat(RegIndex reg) const override
616c668,669
< VecPredRegContainer& getWritableVecPredRegFlat(const RegIndex& reg)
---
> VecPredRegContainer &
> getWritableVecPredRegFlat(RegIndex reg) override
621c674,675
< void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val)
---
> void
> setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override
627,628c681,682
< RegVal readCCRegFlat(int idx) { return ccRegs[idx]; }
< void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; }
---
> RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
> void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; }
630,631c684,688
< RegVal readCCRegFlat(int idx)
< { panic("readCCRegFlat w/no CC regs!\n"); }
---
> RegVal
> readCCRegFlat(RegIndex idx) const override
> {
> panic("readCCRegFlat w/no CC regs!\n");
> }
633,634c690,694
< void setCCRegFlat(int idx, RegVal val)
< { panic("setCCRegFlat w/no CC regs!\n"); }
---
> void
> setCCRegFlat(RegIndex idx, RegVal val) override
> {
> panic("setCCRegFlat w/no CC regs!\n");
> }
< * ThreadContext interface so that a ProxyThreadContext class can be
< * made using SimpleThread as the template parameter (see
< * thread_context.hh). It adds to the ThreadState object by adding all
---
> * ThreadContext interface and adds to the ThreadState object by adding all
99c97
< class SimpleThread : public ThreadState
---
> class SimpleThread : public ThreadState, public ThreadContext
127c125
< return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
---
> return csprintf("%s.[tid:%i]", baseCpu->name(), threadId());
130,131d127
< ProxyThreadContext<SimpleThread> *tc;
<
149c145
< virtual ~SimpleThread();
---
> virtual ~SimpleThread() {}
151c147
< virtual void takeOverFrom(ThreadContext *oldContext);
---
> void takeOverFrom(ThreadContext *oldContext) override;
153c149
< void regStats(const std::string &name);
---
> void regStats(const std::string &name) override;
170c166
< ThreadContext *getTC() { return tc; }
---
> ThreadContext *getTC() { return this; }
188c184
< void dumpFuncProfile();
---
> void dumpFuncProfile() override;
198c194
< BaseCPU *getCpuPtr() { return baseCpu; }
---
> BaseCPU *getCpuPtr() override { return baseCpu; }
200c196,201
< BaseTLB *getITBPtr() { return itb; }
---
> int cpuId() const override { return ThreadState::cpuId(); }
> uint32_t socketId() const override { return ThreadState::socketId(); }
> int threadId() const override { return ThreadState::threadId(); }
> void setThreadId(int id) override { ThreadState::setThreadId(id); }
> ContextID contextId() const override { return ThreadState::contextId(); }
> void setContextId(ContextID id) override { ThreadState::setContextId(id); }
202c203
< BaseTLB *getDTBPtr() { return dtb; }
---
> BaseTLB *getITBPtr() override { return itb; }
204c205
< CheckerCPU *getCheckerCpuPtr() { return NULL; }
---
> BaseTLB *getDTBPtr() override { return dtb; }
206c207
< TheISA::ISA *getIsaPtr() { return isa; }
---
> CheckerCPU *getCheckerCpuPtr() override { return NULL; }
208c209
< TheISA::Decoder *getDecoderPtr() { return &decoder; }
---
> TheISA::ISA *getIsaPtr() override { return isa; }
210c211
< System *getSystemPtr() { return system; }
---
> TheISA::Decoder *getDecoderPtr() override { return &decoder; }
212c213
< Status status() const { return _status; }
---
> System *getSystemPtr() override { return system; }
214c215,219
< void setStatus(Status newStatus) { _status = newStatus; }
---
> TheISA::Kernel::Statistics *
> getKernelStats()
> {
> return ThreadState::getKernelStats();
> }
215a221,241
> PortProxy &getPhysProxy() { return ThreadState::getPhysProxy(); }
> FSTranslatingPortProxy &
> getVirtProxy()
> {
> return ThreadState::getVirtProxy();
> }
>
> void initMemProxies(ThreadContext *tc) { ThreadState::initMemProxies(tc); }
> SETranslatingPortProxy &
> getMemProxy()
> {
> return ThreadState::getMemProxy();
> }
>
> Process *getProcessPtr() { return ThreadState::getProcessPtr(); }
> void setProcessPtr(Process *p) override { ThreadState::setProcessPtr(p); }
>
> Status status() const override { return _status; }
>
> void setStatus(Status newStatus) override { _status = newStatus; }
>
217c243
< void activate();
---
> void activate() override;
220c246
< void suspend();
---
> void suspend() override;
223c249
< void halt();
---
> void halt() override;
225c251,255
< void copyArchRegs(ThreadContext *tc);
---
> EndQuiesceEvent *
> getQuiesceEvent() override
> {
> return ThreadState::getQuiesceEvent();
> }
227c257,258
< void clearArchRegs()
---
> Tick
> readLastActivate() override
228a260,274
> return ThreadState::readLastActivate();
> }
> Tick
> readLastSuspend() override
> {
> return ThreadState::readLastSuspend();
> }
>
> void profileClear() override { ThreadState::profileClear(); }
> void profileSample() override { ThreadState::profileSample(); }
>
> void copyArchRegs(ThreadContext *tc) override;
>
> void clearArchRegs() override
> {
248c294
< readIntReg(int reg_idx)
---
> readIntReg(RegIndex reg_idx) const override
259c305
< readFloatReg(int reg_idx)
---
> readFloatReg(RegIndex reg_idx) const override
270c316
< readVecReg(const RegId& reg) const
---
> readVecReg(const RegId& reg) const override
281c327
< getWritableVecReg(const RegId& reg)
---
> getWritableVecReg(const RegId& reg) override
308,309c354,357
< readVec8BitLaneReg(const RegId& reg) const
< { return readVecLane<uint8_t>(reg); }
---
> readVec8BitLaneReg(const RegId ®) const override
> {
> return readVecLane<uint8_t>(reg);
> }
313,314c361,364
< readVec16BitLaneReg(const RegId& reg) const
< { return readVecLane<uint16_t>(reg); }
---
> readVec16BitLaneReg(const RegId ®) const override
> {
> return readVecLane<uint16_t>(reg);
> }
318,319c368,371
< readVec32BitLaneReg(const RegId& reg) const
< { return readVecLane<uint32_t>(reg); }
---
> readVec32BitLaneReg(const RegId ®) const override
> {
> return readVecLane<uint32_t>(reg);
> }
323,324c375,378
< readVec64BitLaneReg(const RegId& reg) const
< { return readVecLane<uint64_t>(reg); }
---
> readVec64BitLaneReg(const RegId ®) const override
> {
> return readVecLane<uint64_t>(reg);
> }
328c382,383
< void setVecLaneT(const RegId& reg, const LD& val)
---
> void
> setVecLaneT(const RegId ®, const LD &val)
336,347c391,413
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::Byte>& val)
< { return setVecLaneT(reg, val); }
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::TwoByte>& val)
< { return setVecLaneT(reg, val); }
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::FourByte>& val)
< { return setVecLaneT(reg, val); }
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::EightByte>& val)
< { return setVecLaneT(reg, val); }
---
> virtual void
> setVecLane(const RegId ®, const LaneData<LaneSize::Byte> &val) override
> {
> return setVecLaneT(reg, val);
> }
> virtual void
> setVecLane(const RegId ®,
> const LaneData<LaneSize::TwoByte> &val) override
> {
> return setVecLaneT(reg, val);
> }
> virtual void
> setVecLane(const RegId ®,
> const LaneData<LaneSize::FourByte> &val) override
> {
> return setVecLaneT(reg, val);
> }
> virtual void
> setVecLane(const RegId ®,
> const LaneData<LaneSize::EightByte> &val) override
> {
> return setVecLaneT(reg, val);
> }
350c416,417
< const VecElem& readVecElem(const RegId& reg) const
---
> const VecElem &
> readVecElem(const RegId ®) const override
360,361c427,428
< const VecPredRegContainer&
< readVecPredReg(const RegId& reg) const
---
> const VecPredRegContainer &
> readVecPredReg(const RegId ®) const override
371,372c438,439
< VecPredRegContainer&
< getWritableVecPredReg(const RegId& reg)
---
> VecPredRegContainer &
> getWritableVecPredReg(const RegId ®) override
384c451
< readCCReg(int reg_idx)
---
> readCCReg(RegIndex reg_idx) const override
401c468
< setIntReg(int reg_idx, RegVal val)
---
> setIntReg(RegIndex reg_idx, RegVal val) override
411c478
< setFloatReg(int reg_idx, RegVal val)
---
> setFloatReg(RegIndex reg_idx, RegVal val) override
424c491
< setVecReg(const RegId& reg, const VecRegContainer& val)
---
> setVecReg(const RegId ®, const VecRegContainer &val) override
434c501
< setVecElem(const RegId& reg, const VecElem& val)
---
> setVecElem(const RegId ®, const VecElem &val) override
444c511
< setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
---
> setVecPredReg(const RegId ®, const VecPredRegContainer &val) override
454c521
< setCCReg(int reg_idx, RegVal val)
---
> setCCReg(RegIndex reg_idx, RegVal val) override
467,471c534,535
< TheISA::PCState
< pcState()
< {
< return _pcState;
< }
---
> TheISA::PCState pcState() const override { return _pcState; }
> void pcState(const TheISA::PCState &val) override { _pcState = val; }
474c538
< pcState(const TheISA::PCState &val)
---
> pcStateNoRecord(const TheISA::PCState &val) override
479,483c543,547
< void
< pcStateNoRecord(const TheISA::PCState &val)
< {
< _pcState = val;
< }
---
> Addr instAddr() const override { return _pcState.instAddr(); }
> Addr nextInstAddr() const override { return _pcState.nextInstAddr(); }
> MicroPC microPC() const override { return _pcState.microPC(); }
> bool readPredicate() const { return predicate; }
> void setPredicate(bool val) { predicate = val; }
485,486c549,550
< Addr
< instAddr()
---
> RegVal
> readMiscRegNoEffect(RegIndex misc_reg) const override
488c552
< return _pcState.instAddr();
---
> return isa->readMiscRegNoEffect(misc_reg);
491,492c555,556
< Addr
< nextInstAddr()
---
> RegVal
> readMiscReg(RegIndex misc_reg) override
494c558
< return _pcState.nextInstAddr();
---
> return isa->readMiscReg(misc_reg, this);
498c562
< setNPC(Addr val)
---
> setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
500c564
< _pcState.setNPC(val);
---
> return isa->setMiscRegNoEffect(misc_reg, val);
503,504c567,568
< MicroPC
< microPC()
---
> void
> setMiscReg(RegIndex misc_reg, RegVal val) override
506c570
< return _pcState.microPC();
---
> return isa->setMiscReg(misc_reg, val, this);
509c573,574
< bool readPredicate()
---
> RegId
> flattenRegId(const RegId& regId) const override
511c576
< return predicate;
---
> return isa->flattenRegId(regId);
514,517c579
< void setPredicate(bool val)
< {
< predicate = val;
< }
---
> unsigned readStCondFailures() const override { return storeCondFailures; }
519,520c581,582
< RegVal
< readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
---
> void
> setStCondFailures(unsigned sc_failures) override
522c584
< return isa->readMiscRegNoEffect(misc_reg);
---
> storeCondFailures = sc_failures;
525,526c587,588
< RegVal
< readMiscReg(int misc_reg, ThreadID tid=0)
---
> Counter
> readFuncExeInst() const override
528c590
< return isa->readMiscReg(misc_reg, tc);
---
> return ThreadState::readFuncExeInst();
532c594
< setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0)
---
> syscall(int64_t callnum, Fault *fault) override
534c596
< return isa->setMiscRegNoEffect(misc_reg, val);
---
> process->syscall(callnum, this, fault);
536a599
> RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; }
538c601
< setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0)
---
> setIntRegFlat(RegIndex idx, RegVal val) override
540c603
< return isa->setMiscReg(misc_reg, val, tc);
---
> intRegs[idx] = val;
543,544c606,607
< RegId
< flattenRegId(const RegId& regId) const
---
> RegVal
> readFloatRegFlat(RegIndex idx) const override
546c609
< return isa->flattenRegId(regId);
---
> return floatRegs[idx];
548,553d610
<
< unsigned readStCondFailures() { return storeCondFailures; }
<
< void setStCondFailures(unsigned sc_failures)
< { storeCondFailures = sc_failures; }
<
555c612
< syscall(int64_t callnum, Fault *fault)
---
> setFloatRegFlat(RegIndex idx, RegVal val) override
557c614
< process->syscall(callnum, tc, fault);
---
> floatRegs[idx] = val;
560,565d616
< RegVal readIntRegFlat(int idx) { return intRegs[idx]; }
< void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; }
<
< RegVal readFloatRegFlat(int idx) { return floatRegs[idx]; }
< void setFloatRegFlat(int idx, RegVal val) { floatRegs[idx] = val; }
<
567c618
< readVecRegFlat(const RegIndex& reg) const
---
> readVecRegFlat(RegIndex reg) const override
573c624
< getWritableVecRegFlat(const RegIndex& reg)
---
> getWritableVecRegFlat(RegIndex reg) override
579c630
< setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
---
> setVecRegFlat(RegIndex reg, const VecRegContainer &val) override
586c637
< readVecLaneFlat(const RegIndex& reg, int lId) const
---
> readVecLaneFlat(RegIndex reg, int lId) const
593c644
< setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
---
> setVecLaneFlat(RegIndex reg, int lId, const LD &val)
599c650
< readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const
---
> readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
605,606c656,657
< setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
< const VecElem val)
---
> setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
> const VecElem &val) override
611c662,663
< const VecPredRegContainer& readVecPredRegFlat(const RegIndex& reg) const
---
> const VecPredRegContainer &
> readVecPredRegFlat(RegIndex reg) const override
616c668,669
< VecPredRegContainer& getWritableVecPredRegFlat(const RegIndex& reg)
---
> VecPredRegContainer &
> getWritableVecPredRegFlat(RegIndex reg) override
621c674,675
< void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val)
---
> void
> setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override
627,628c681,682
< RegVal readCCRegFlat(int idx) { return ccRegs[idx]; }
< void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; }
---
> RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
> void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; }
630,631c684,688
< RegVal readCCRegFlat(int idx)
< { panic("readCCRegFlat w/no CC regs!\n"); }
---
> RegVal
> readCCRegFlat(RegIndex idx) const override
> {
> panic("readCCRegFlat w/no CC regs!\n");
> }
633,634c690,694
< void setCCRegFlat(int idx, RegVal val)
< { panic("setCCRegFlat w/no CC regs!\n"); }
---
> void
> setCCRegFlat(RegIndex idx, RegVal val) override
> {
> panic("setCCRegFlat w/no CC regs!\n");
> }