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< * Copyright (c) 2011-2012, 2016 ARM Limited
---
> * Copyright (c) 2011-2012, 2016-2018 ARM Limited
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> #include "debug/VecPredRegs.hh"
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> using VecPredRegContainer = TheISA::VecPredRegContainer;
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> VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
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> for (int i = 0; i < TheISA::NumVecPredRegs; i++) {
> vecPredRegs[i].reset();
> }
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< reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print());
---
> reg.index(), flatIndex, regVal.print());
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< reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print());
---
> reg.index(), flatIndex, regVal.print());
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> const VecPredRegContainer&
> readVecPredReg(const RegId& reg) const
> {
> int flatIndex = isa->flattenVecPredIndex(reg.index());
> assert(flatIndex < TheISA::NumVecPredRegs);
> const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex);
> DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
> reg.index(), flatIndex, regVal.print());
> return regVal;
> }
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> VecPredRegContainer&
> getWritableVecPredReg(const RegId& reg)
> {
> int flatIndex = isa->flattenVecPredIndex(reg.index());
> assert(flatIndex < TheISA::NumVecPredRegs);
> VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex);
> DPRINTF(VecPredRegs,
> "Reading predicate reg %d (%d) as %s for modify.\n",
> reg.index(), flatIndex, regVal.print());
> return regVal;
> }
>
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> setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
> {
> int flatIndex = isa->flattenVecPredIndex(reg.index());
> assert(flatIndex < TheISA::NumVecPredRegs);
> setVecPredRegFlat(flatIndex, val);
> DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
> reg.index(), flatIndex, val.print());
> }
>
> void
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> const VecPredRegContainer& readVecPredRegFlat(const RegIndex& reg) const
> {
> return vecPredRegs[reg];
> }
>
> VecPredRegContainer& getWritableVecPredRegFlat(const RegIndex& reg)
> {
> return vecPredRegs[reg];
> }
>
> void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val)
> {
> vecPredRegs[reg] = val;
> }
>