1/* 2 * Copyright (c) 2011 ARM Limited
| 1/* 2 * Copyright (c) 2011 ARM Limited
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| 3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 * Nathan Binkert 42 */ 43 44#ifndef __CPU_SIMPLE_THREAD_HH__ 45#define __CPU_SIMPLE_THREAD_HH__ 46 47#include "arch/decoder.hh" 48#include "arch/isa.hh" 49#include "arch/isa_traits.hh" 50#include "arch/registers.hh" 51#include "arch/tlb.hh" 52#include "arch/types.hh" 53#include "base/types.hh" 54#include "config/the_isa.hh" 55#include "cpu/thread_context.hh" 56#include "cpu/thread_state.hh"
| 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2001-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 */ 44 45#ifndef __CPU_SIMPLE_THREAD_HH__ 46#define __CPU_SIMPLE_THREAD_HH__ 47 48#include "arch/decoder.hh" 49#include "arch/isa.hh" 50#include "arch/isa_traits.hh" 51#include "arch/registers.hh" 52#include "arch/tlb.hh" 53#include "arch/types.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh"
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| 58#include "debug/CCRegs.hh"
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57#include "debug/FloatRegs.hh" 58#include "debug/IntRegs.hh" 59#include "mem/page_table.hh" 60#include "mem/request.hh" 61#include "sim/byteswap.hh" 62#include "sim/eventq.hh" 63#include "sim/process.hh" 64#include "sim/serialize.hh" 65#include "sim/system.hh" 66 67class BaseCPU; 68class CheckerCPU; 69 70class FunctionProfile; 71class ProfileNode; 72 73namespace TheISA { 74 namespace Kernel { 75 class Statistics; 76 } 77} 78 79/** 80 * The SimpleThread object provides a combination of the ThreadState 81 * object and the ThreadContext interface. It implements the 82 * ThreadContext interface so that a ProxyThreadContext class can be 83 * made using SimpleThread as the template parameter (see 84 * thread_context.hh). It adds to the ThreadState object by adding all 85 * the objects needed for simple functional execution, including a 86 * simple architectural register file, and pointers to the ITB and DTB 87 * in full system mode. For CPU models that do not need more advanced 88 * ways to hold state (i.e. a separate physical register file, or 89 * separate fetch and commit PC's), this SimpleThread class provides 90 * all the necessary state for full architecture-level functional 91 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 92 * examples. 93 */ 94 95class SimpleThread : public ThreadState 96{ 97 protected: 98 typedef TheISA::MachInst MachInst; 99 typedef TheISA::MiscReg MiscReg; 100 typedef TheISA::FloatReg FloatReg; 101 typedef TheISA::FloatRegBits FloatRegBits;
| 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" 61#include "mem/page_table.hh" 62#include "mem/request.hh" 63#include "sim/byteswap.hh" 64#include "sim/eventq.hh" 65#include "sim/process.hh" 66#include "sim/serialize.hh" 67#include "sim/system.hh" 68 69class BaseCPU; 70class CheckerCPU; 71 72class FunctionProfile; 73class ProfileNode; 74 75namespace TheISA { 76 namespace Kernel { 77 class Statistics; 78 } 79} 80 81/** 82 * The SimpleThread object provides a combination of the ThreadState 83 * object and the ThreadContext interface. It implements the 84 * ThreadContext interface so that a ProxyThreadContext class can be 85 * made using SimpleThread as the template parameter (see 86 * thread_context.hh). It adds to the ThreadState object by adding all 87 * the objects needed for simple functional execution, including a 88 * simple architectural register file, and pointers to the ITB and DTB 89 * in full system mode. For CPU models that do not need more advanced 90 * ways to hold state (i.e. a separate physical register file, or 91 * separate fetch and commit PC's), this SimpleThread class provides 92 * all the necessary state for full architecture-level functional 93 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 94 * examples. 95 */ 96 97class SimpleThread : public ThreadState 98{ 99 protected: 100 typedef TheISA::MachInst MachInst; 101 typedef TheISA::MiscReg MiscReg; 102 typedef TheISA::FloatReg FloatReg; 103 typedef TheISA::FloatRegBits FloatRegBits;
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| 104 typedef TheISA::CCReg CCReg;
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102 public: 103 typedef ThreadContext::Status Status; 104 105 protected: 106 union { 107 FloatReg f[TheISA::NumFloatRegs]; 108 FloatRegBits i[TheISA::NumFloatRegs]; 109 } floatRegs; 110 TheISA::IntReg intRegs[TheISA::NumIntRegs];
| 105 public: 106 typedef ThreadContext::Status Status; 107 108 protected: 109 union { 110 FloatReg f[TheISA::NumFloatRegs]; 111 FloatRegBits i[TheISA::NumFloatRegs]; 112 } floatRegs; 113 TheISA::IntReg intRegs[TheISA::NumIntRegs];
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| 114#ifdef ISA_HAS_CC_REGS 115 TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 116#endif
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111 TheISA::ISA *const isa; // one "instance" of the current ISA. 112 113 TheISA::PCState _pcState; 114 115 /** Did this instruction execute or is it predicated false */ 116 bool predicate; 117 118 public: 119 std::string name() const 120 { 121 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 122 } 123 124 ProxyThreadContext<SimpleThread> *tc; 125 126 System *system; 127 128 TheISA::TLB *itb; 129 TheISA::TLB *dtb; 130 131 TheISA::Decoder decoder; 132 133 // constructor: initialize SimpleThread from given process structure 134 // FS 135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 136 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa, 137 bool use_kernel_stats = true); 138 // SE 139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 140 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb, 141 TheISA::ISA *_isa); 142 143 virtual ~SimpleThread(); 144 145 virtual void takeOverFrom(ThreadContext *oldContext); 146 147 void regStats(const std::string &name); 148 149 void copyState(ThreadContext *oldContext); 150 151 void serialize(std::ostream &os); 152 void unserialize(Checkpoint *cp, const std::string §ion); 153 void startup(); 154 155 /*************************************************************** 156 * SimpleThread functions to provide CPU with access to various 157 * state. 158 **************************************************************/ 159 160 /** Returns the pointer to this SimpleThread's ThreadContext. Used 161 * when a ThreadContext must be passed to objects outside of the 162 * CPU. 163 */ 164 ThreadContext *getTC() { return tc; } 165 166 void demapPage(Addr vaddr, uint64_t asn) 167 { 168 itb->demapPage(vaddr, asn); 169 dtb->demapPage(vaddr, asn); 170 } 171 172 void demapInstPage(Addr vaddr, uint64_t asn) 173 { 174 itb->demapPage(vaddr, asn); 175 } 176 177 void demapDataPage(Addr vaddr, uint64_t asn) 178 { 179 dtb->demapPage(vaddr, asn); 180 } 181 182 void dumpFuncProfile(); 183 184 Fault hwrei(); 185 186 bool simPalCheck(int palFunc); 187 188 /******************************************* 189 * ThreadContext interface functions. 190 ******************************************/ 191 192 BaseCPU *getCpuPtr() { return baseCpu; } 193 194 TheISA::TLB *getITBPtr() { return itb; } 195 196 TheISA::TLB *getDTBPtr() { return dtb; } 197 198 CheckerCPU *getCheckerCpuPtr() { return NULL; } 199 200 TheISA::Decoder *getDecoderPtr() { return &decoder; } 201 202 System *getSystemPtr() { return system; } 203 204 Status status() const { return _status; } 205 206 void setStatus(Status newStatus) { _status = newStatus; } 207 208 /// Set the status to Active. Optional delay indicates number of 209 /// cycles to wait before beginning execution. 210 void activate(Cycles delay = Cycles(1)); 211 212 /// Set the status to Suspended. 213 void suspend(); 214 215 /// Set the status to Halted. 216 void halt(); 217 218 virtual bool misspeculating(); 219 220 void copyArchRegs(ThreadContext *tc); 221 222 void clearArchRegs() 223 { 224 _pcState = 0; 225 memset(intRegs, 0, sizeof(intRegs)); 226 memset(floatRegs.i, 0, sizeof(floatRegs.i));
| 117 TheISA::ISA *const isa; // one "instance" of the current ISA. 118 119 TheISA::PCState _pcState; 120 121 /** Did this instruction execute or is it predicated false */ 122 bool predicate; 123 124 public: 125 std::string name() const 126 { 127 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 128 } 129 130 ProxyThreadContext<SimpleThread> *tc; 131 132 System *system; 133 134 TheISA::TLB *itb; 135 TheISA::TLB *dtb; 136 137 TheISA::Decoder decoder; 138 139 // constructor: initialize SimpleThread from given process structure 140 // FS 141 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 142 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa, 143 bool use_kernel_stats = true); 144 // SE 145 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 146 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb, 147 TheISA::ISA *_isa); 148 149 virtual ~SimpleThread(); 150 151 virtual void takeOverFrom(ThreadContext *oldContext); 152 153 void regStats(const std::string &name); 154 155 void copyState(ThreadContext *oldContext); 156 157 void serialize(std::ostream &os); 158 void unserialize(Checkpoint *cp, const std::string §ion); 159 void startup(); 160 161 /*************************************************************** 162 * SimpleThread functions to provide CPU with access to various 163 * state. 164 **************************************************************/ 165 166 /** Returns the pointer to this SimpleThread's ThreadContext. Used 167 * when a ThreadContext must be passed to objects outside of the 168 * CPU. 169 */ 170 ThreadContext *getTC() { return tc; } 171 172 void demapPage(Addr vaddr, uint64_t asn) 173 { 174 itb->demapPage(vaddr, asn); 175 dtb->demapPage(vaddr, asn); 176 } 177 178 void demapInstPage(Addr vaddr, uint64_t asn) 179 { 180 itb->demapPage(vaddr, asn); 181 } 182 183 void demapDataPage(Addr vaddr, uint64_t asn) 184 { 185 dtb->demapPage(vaddr, asn); 186 } 187 188 void dumpFuncProfile(); 189 190 Fault hwrei(); 191 192 bool simPalCheck(int palFunc); 193 194 /******************************************* 195 * ThreadContext interface functions. 196 ******************************************/ 197 198 BaseCPU *getCpuPtr() { return baseCpu; } 199 200 TheISA::TLB *getITBPtr() { return itb; } 201 202 TheISA::TLB *getDTBPtr() { return dtb; } 203 204 CheckerCPU *getCheckerCpuPtr() { return NULL; } 205 206 TheISA::Decoder *getDecoderPtr() { return &decoder; } 207 208 System *getSystemPtr() { return system; } 209 210 Status status() const { return _status; } 211 212 void setStatus(Status newStatus) { _status = newStatus; } 213 214 /// Set the status to Active. Optional delay indicates number of 215 /// cycles to wait before beginning execution. 216 void activate(Cycles delay = Cycles(1)); 217 218 /// Set the status to Suspended. 219 void suspend(); 220 221 /// Set the status to Halted. 222 void halt(); 223 224 virtual bool misspeculating(); 225 226 void copyArchRegs(ThreadContext *tc); 227 228 void clearArchRegs() 229 { 230 _pcState = 0; 231 memset(intRegs, 0, sizeof(intRegs)); 232 memset(floatRegs.i, 0, sizeof(floatRegs.i));
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| 233#ifdef ISA_HAS_CC_REGS 234 memset(ccRegs, 0, sizeof(ccRegs)); 235#endif
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227 isa->clear(); 228 } 229 230 // 231 // New accessors for new decoder. 232 // 233 uint64_t readIntReg(int reg_idx) 234 { 235 int flatIndex = isa->flattenIntIndex(reg_idx); 236 assert(flatIndex < TheISA::NumIntRegs); 237 uint64_t regVal(readIntRegFlat(flatIndex)); 238 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 239 reg_idx, flatIndex, regVal); 240 return regVal; 241 } 242 243 FloatReg readFloatReg(int reg_idx) 244 { 245 int flatIndex = isa->flattenFloatIndex(reg_idx); 246 assert(flatIndex < TheISA::NumFloatRegs); 247 FloatReg regVal(readFloatRegFlat(flatIndex)); 248 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 249 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 250 return regVal; 251 } 252 253 FloatRegBits readFloatRegBits(int reg_idx) 254 { 255 int flatIndex = isa->flattenFloatIndex(reg_idx); 256 assert(flatIndex < TheISA::NumFloatRegs); 257 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 258 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 259 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 260 return regVal; 261 } 262
| 236 isa->clear(); 237 } 238 239 // 240 // New accessors for new decoder. 241 // 242 uint64_t readIntReg(int reg_idx) 243 { 244 int flatIndex = isa->flattenIntIndex(reg_idx); 245 assert(flatIndex < TheISA::NumIntRegs); 246 uint64_t regVal(readIntRegFlat(flatIndex)); 247 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 248 reg_idx, flatIndex, regVal); 249 return regVal; 250 } 251 252 FloatReg readFloatReg(int reg_idx) 253 { 254 int flatIndex = isa->flattenFloatIndex(reg_idx); 255 assert(flatIndex < TheISA::NumFloatRegs); 256 FloatReg regVal(readFloatRegFlat(flatIndex)); 257 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 258 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 259 return regVal; 260 } 261 262 FloatRegBits readFloatRegBits(int reg_idx) 263 { 264 int flatIndex = isa->flattenFloatIndex(reg_idx); 265 assert(flatIndex < TheISA::NumFloatRegs); 266 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 267 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 268 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 269 return regVal; 270 } 271
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| 272 CCReg readCCReg(int reg_idx) 273 { 274#ifdef ISA_HAS_CC_REGS 275 int flatIndex = isa->flattenCCIndex(reg_idx); 276 assert(flatIndex < TheISA::NumCCRegs); 277 uint64_t regVal(readCCRegFlat(flatIndex)); 278 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 279 reg_idx, flatIndex, regVal); 280 return regVal; 281#else 282 panic("Tried to read a CC register."); 283 return 0; 284#endif 285 } 286
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263 void setIntReg(int reg_idx, uint64_t val) 264 { 265 int flatIndex = isa->flattenIntIndex(reg_idx); 266 assert(flatIndex < TheISA::NumIntRegs); 267 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 268 reg_idx, flatIndex, val); 269 setIntRegFlat(flatIndex, val); 270 } 271 272 void setFloatReg(int reg_idx, FloatReg val) 273 { 274 int flatIndex = isa->flattenFloatIndex(reg_idx); 275 assert(flatIndex < TheISA::NumFloatRegs); 276 setFloatRegFlat(flatIndex, val); 277 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 278 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 279 } 280 281 void setFloatRegBits(int reg_idx, FloatRegBits val) 282 { 283 int flatIndex = isa->flattenFloatIndex(reg_idx); 284 assert(flatIndex < TheISA::NumFloatRegs); 285 // XXX: Fix array out of bounds compiler error for gem5.fast 286 // when checkercpu enabled 287 if (flatIndex < TheISA::NumFloatRegs) 288 setFloatRegBitsFlat(flatIndex, val); 289 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 290 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 291 } 292
| 287 void setIntReg(int reg_idx, uint64_t val) 288 { 289 int flatIndex = isa->flattenIntIndex(reg_idx); 290 assert(flatIndex < TheISA::NumIntRegs); 291 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 292 reg_idx, flatIndex, val); 293 setIntRegFlat(flatIndex, val); 294 } 295 296 void setFloatReg(int reg_idx, FloatReg val) 297 { 298 int flatIndex = isa->flattenFloatIndex(reg_idx); 299 assert(flatIndex < TheISA::NumFloatRegs); 300 setFloatRegFlat(flatIndex, val); 301 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 302 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 303 } 304 305 void setFloatRegBits(int reg_idx, FloatRegBits val) 306 { 307 int flatIndex = isa->flattenFloatIndex(reg_idx); 308 assert(flatIndex < TheISA::NumFloatRegs); 309 // XXX: Fix array out of bounds compiler error for gem5.fast 310 // when checkercpu enabled 311 if (flatIndex < TheISA::NumFloatRegs) 312 setFloatRegBitsFlat(flatIndex, val); 313 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 314 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 315 } 316
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| 317 void setCCReg(int reg_idx, CCReg val) 318 { 319#ifdef ISA_HAS_CC_REGS 320 int flatIndex = isa->flattenCCIndex(reg_idx); 321 assert(flatIndex < TheISA::NumCCRegs); 322 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 323 reg_idx, flatIndex, val); 324 setCCRegFlat(flatIndex, val); 325#else 326 panic("Tried to set a CC register."); 327#endif 328 } 329
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293 TheISA::PCState 294 pcState() 295 { 296 return _pcState; 297 } 298 299 void 300 pcState(const TheISA::PCState &val) 301 { 302 _pcState = val; 303 } 304 305 void 306 pcStateNoRecord(const TheISA::PCState &val) 307 { 308 _pcState = val; 309 } 310 311 Addr 312 instAddr() 313 { 314 return _pcState.instAddr(); 315 } 316 317 Addr 318 nextInstAddr() 319 { 320 return _pcState.nextInstAddr(); 321 } 322 323 MicroPC 324 microPC() 325 { 326 return _pcState.microPC(); 327 } 328 329 bool readPredicate() 330 { 331 return predicate; 332 } 333 334 void setPredicate(bool val) 335 { 336 predicate = val; 337 } 338 339 MiscReg 340 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 341 { 342 return isa->readMiscRegNoEffect(misc_reg); 343 } 344 345 MiscReg 346 readMiscReg(int misc_reg, ThreadID tid = 0) 347 { 348 return isa->readMiscReg(misc_reg, tc); 349 } 350 351 void 352 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 353 { 354 return isa->setMiscRegNoEffect(misc_reg, val); 355 } 356 357 void 358 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 359 { 360 return isa->setMiscReg(misc_reg, val, tc); 361 } 362 363 int 364 flattenIntIndex(int reg) 365 { 366 return isa->flattenIntIndex(reg); 367 } 368 369 int 370 flattenFloatIndex(int reg) 371 { 372 return isa->flattenFloatIndex(reg); 373 } 374
| 330 TheISA::PCState 331 pcState() 332 { 333 return _pcState; 334 } 335 336 void 337 pcState(const TheISA::PCState &val) 338 { 339 _pcState = val; 340 } 341 342 void 343 pcStateNoRecord(const TheISA::PCState &val) 344 { 345 _pcState = val; 346 } 347 348 Addr 349 instAddr() 350 { 351 return _pcState.instAddr(); 352 } 353 354 Addr 355 nextInstAddr() 356 { 357 return _pcState.nextInstAddr(); 358 } 359 360 MicroPC 361 microPC() 362 { 363 return _pcState.microPC(); 364 } 365 366 bool readPredicate() 367 { 368 return predicate; 369 } 370 371 void setPredicate(bool val) 372 { 373 predicate = val; 374 } 375 376 MiscReg 377 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 378 { 379 return isa->readMiscRegNoEffect(misc_reg); 380 } 381 382 MiscReg 383 readMiscReg(int misc_reg, ThreadID tid = 0) 384 { 385 return isa->readMiscReg(misc_reg, tc); 386 } 387 388 void 389 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 390 { 391 return isa->setMiscRegNoEffect(misc_reg, val); 392 } 393 394 void 395 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 396 { 397 return isa->setMiscReg(misc_reg, val, tc); 398 } 399 400 int 401 flattenIntIndex(int reg) 402 { 403 return isa->flattenIntIndex(reg); 404 } 405 406 int 407 flattenFloatIndex(int reg) 408 { 409 return isa->flattenFloatIndex(reg); 410 } 411
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| 412 int 413 flattenCCIndex(int reg) 414 { 415 return isa->flattenCCIndex(reg); 416 } 417
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375 unsigned readStCondFailures() { return storeCondFailures; } 376 377 void setStCondFailures(unsigned sc_failures) 378 { storeCondFailures = sc_failures; } 379 380 void syscall(int64_t callnum) 381 { 382 process->syscall(callnum, tc); 383 } 384 385 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 386 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 387 388 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 389 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 390 391 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 392 void setFloatRegBitsFlat(int idx, FloatRegBits val) { 393 floatRegs.i[idx] = val; 394 } 395
| 418 unsigned readStCondFailures() { return storeCondFailures; } 419 420 void setStCondFailures(unsigned sc_failures) 421 { storeCondFailures = sc_failures; } 422 423 void syscall(int64_t callnum) 424 { 425 process->syscall(callnum, tc); 426 } 427 428 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 429 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 430 431 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 432 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 433 434 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 435 void setFloatRegBitsFlat(int idx, FloatRegBits val) { 436 floatRegs.i[idx] = val; 437 } 438
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| 439#ifdef ISA_HAS_CC_REGS 440 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 441 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 442#else 443 CCReg readCCRegFlat(int idx) 444 { panic("readCCRegFlat w/no CC regs!\n"); } 445 446 void setCCRegFlat(int idx, CCReg val) 447 { panic("setCCRegFlat w/no CC regs!\n"); } 448#endif
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396}; 397 398 399// for non-speculative execution context, spec_mode is always false 400inline bool 401SimpleThread::misspeculating() 402{ 403 return false; 404} 405 406#endif // __CPU_CPU_EXEC_CONTEXT_HH__
| 449}; 450 451 452// for non-speculative execution context, spec_mode is always false 453inline bool 454SimpleThread::misspeculating() 455{ 456 return false; 457} 458 459#endif // __CPU_CPU_EXEC_CONTEXT_HH__
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