1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Nathan Binkert
42 */
43
44#ifndef __CPU_SIMPLE_THREAD_HH__
45#define __CPU_SIMPLE_THREAD_HH__
46
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Nathan Binkert
42 */
43
44#ifndef __CPU_SIMPLE_THREAD_HH__
45#define __CPU_SIMPLE_THREAD_HH__
46
|
| 47#include "arch/decoder.hh"
|
47#include "arch/isa.hh"
48#include "arch/isa_traits.hh"
49#include "arch/registers.hh"
50#include "arch/tlb.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
| 48#include "arch/isa.hh"
49#include "arch/isa_traits.hh"
50#include "arch/registers.hh"
51#include "arch/tlb.hh"
52#include "arch/types.hh"
53#include "base/types.hh"
54#include "config/the_isa.hh"
|
54#include "cpu/decode.hh"
| |
55#include "cpu/thread_context.hh"
56#include "cpu/thread_state.hh"
57#include "debug/FloatRegs.hh"
58#include "debug/IntRegs.hh"
59#include "mem/page_table.hh"
60#include "mem/request.hh"
61#include "sim/byteswap.hh"
62#include "sim/eventq.hh"
63#include "sim/process.hh"
64#include "sim/serialize.hh"
65#include "sim/system.hh"
66
67class BaseCPU;
68class CheckerCPU;
69
70class FunctionProfile;
71class ProfileNode;
72
73namespace TheISA {
74 namespace Kernel {
75 class Statistics;
76 }
77}
78
79/**
80 * The SimpleThread object provides a combination of the ThreadState
81 * object and the ThreadContext interface. It implements the
82 * ThreadContext interface so that a ProxyThreadContext class can be
83 * made using SimpleThread as the template parameter (see
84 * thread_context.hh). It adds to the ThreadState object by adding all
85 * the objects needed for simple functional execution, including a
86 * simple architectural register file, and pointers to the ITB and DTB
87 * in full system mode. For CPU models that do not need more advanced
88 * ways to hold state (i.e. a separate physical register file, or
89 * separate fetch and commit PC's), this SimpleThread class provides
90 * all the necessary state for full architecture-level functional
91 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
92 * examples.
93 */
94
95class SimpleThread : public ThreadState
96{
97 protected:
98 typedef TheISA::MachInst MachInst;
99 typedef TheISA::MiscReg MiscReg;
100 typedef TheISA::FloatReg FloatReg;
101 typedef TheISA::FloatRegBits FloatRegBits;
102 public:
103 typedef ThreadContext::Status Status;
104
105 protected:
106 union {
107 FloatReg f[TheISA::NumFloatRegs];
108 FloatRegBits i[TheISA::NumFloatRegs];
109 } floatRegs;
110 TheISA::IntReg intRegs[TheISA::NumIntRegs];
111 TheISA::ISA isa; // one "instance" of the current ISA.
112
113 TheISA::PCState _pcState;
114
115 /** Did this instruction execute or is it predicated false */
116 bool predicate;
117
118 public:
119 std::string name() const
120 {
121 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
122 }
123
124 ProxyThreadContext<SimpleThread> *tc;
125
126 System *system;
127
128 TheISA::TLB *itb;
129 TheISA::TLB *dtb;
130
| 55#include "cpu/thread_context.hh"
56#include "cpu/thread_state.hh"
57#include "debug/FloatRegs.hh"
58#include "debug/IntRegs.hh"
59#include "mem/page_table.hh"
60#include "mem/request.hh"
61#include "sim/byteswap.hh"
62#include "sim/eventq.hh"
63#include "sim/process.hh"
64#include "sim/serialize.hh"
65#include "sim/system.hh"
66
67class BaseCPU;
68class CheckerCPU;
69
70class FunctionProfile;
71class ProfileNode;
72
73namespace TheISA {
74 namespace Kernel {
75 class Statistics;
76 }
77}
78
79/**
80 * The SimpleThread object provides a combination of the ThreadState
81 * object and the ThreadContext interface. It implements the
82 * ThreadContext interface so that a ProxyThreadContext class can be
83 * made using SimpleThread as the template parameter (see
84 * thread_context.hh). It adds to the ThreadState object by adding all
85 * the objects needed for simple functional execution, including a
86 * simple architectural register file, and pointers to the ITB and DTB
87 * in full system mode. For CPU models that do not need more advanced
88 * ways to hold state (i.e. a separate physical register file, or
89 * separate fetch and commit PC's), this SimpleThread class provides
90 * all the necessary state for full architecture-level functional
91 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
92 * examples.
93 */
94
95class SimpleThread : public ThreadState
96{
97 protected:
98 typedef TheISA::MachInst MachInst;
99 typedef TheISA::MiscReg MiscReg;
100 typedef TheISA::FloatReg FloatReg;
101 typedef TheISA::FloatRegBits FloatRegBits;
102 public:
103 typedef ThreadContext::Status Status;
104
105 protected:
106 union {
107 FloatReg f[TheISA::NumFloatRegs];
108 FloatRegBits i[TheISA::NumFloatRegs];
109 } floatRegs;
110 TheISA::IntReg intRegs[TheISA::NumIntRegs];
111 TheISA::ISA isa; // one "instance" of the current ISA.
112
113 TheISA::PCState _pcState;
114
115 /** Did this instruction execute or is it predicated false */
116 bool predicate;
117
118 public:
119 std::string name() const
120 {
121 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
122 }
123
124 ProxyThreadContext<SimpleThread> *tc;
125
126 System *system;
127
128 TheISA::TLB *itb;
129 TheISA::TLB *dtb;
130
|
131 Decoder decoder;
| 131 TheISA::Decoder decoder;
|
132
133 // constructor: initialize SimpleThread from given process structure
134 // FS
135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
136 TheISA::TLB *_itb, TheISA::TLB *_dtb,
137 bool use_kernel_stats = true);
138 // SE
139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
140 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb);
141
142 SimpleThread();
143
144 virtual ~SimpleThread();
145
146 virtual void takeOverFrom(ThreadContext *oldContext);
147
148 void regStats(const std::string &name);
149
150 void copyTC(ThreadContext *context);
151
152 void copyState(ThreadContext *oldContext);
153
154 void serialize(std::ostream &os);
155 void unserialize(Checkpoint *cp, const std::string §ion);
156
157 /***************************************************************
158 * SimpleThread functions to provide CPU with access to various
159 * state.
160 **************************************************************/
161
162 /** Returns the pointer to this SimpleThread's ThreadContext. Used
163 * when a ThreadContext must be passed to objects outside of the
164 * CPU.
165 */
166 ThreadContext *getTC() { return tc; }
167
168 void demapPage(Addr vaddr, uint64_t asn)
169 {
170 itb->demapPage(vaddr, asn);
171 dtb->demapPage(vaddr, asn);
172 }
173
174 void demapInstPage(Addr vaddr, uint64_t asn)
175 {
176 itb->demapPage(vaddr, asn);
177 }
178
179 void demapDataPage(Addr vaddr, uint64_t asn)
180 {
181 dtb->demapPage(vaddr, asn);
182 }
183
184 void dumpFuncProfile();
185
186 Fault hwrei();
187
188 bool simPalCheck(int palFunc);
189
190 /*******************************************
191 * ThreadContext interface functions.
192 ******************************************/
193
194 BaseCPU *getCpuPtr() { return baseCpu; }
195
196 TheISA::TLB *getITBPtr() { return itb; }
197
198 TheISA::TLB *getDTBPtr() { return dtb; }
199
200 CheckerCPU *getCheckerCpuPtr() { return NULL; }
201
| 132
133 // constructor: initialize SimpleThread from given process structure
134 // FS
135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
136 TheISA::TLB *_itb, TheISA::TLB *_dtb,
137 bool use_kernel_stats = true);
138 // SE
139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
140 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb);
141
142 SimpleThread();
143
144 virtual ~SimpleThread();
145
146 virtual void takeOverFrom(ThreadContext *oldContext);
147
148 void regStats(const std::string &name);
149
150 void copyTC(ThreadContext *context);
151
152 void copyState(ThreadContext *oldContext);
153
154 void serialize(std::ostream &os);
155 void unserialize(Checkpoint *cp, const std::string §ion);
156
157 /***************************************************************
158 * SimpleThread functions to provide CPU with access to various
159 * state.
160 **************************************************************/
161
162 /** Returns the pointer to this SimpleThread's ThreadContext. Used
163 * when a ThreadContext must be passed to objects outside of the
164 * CPU.
165 */
166 ThreadContext *getTC() { return tc; }
167
168 void demapPage(Addr vaddr, uint64_t asn)
169 {
170 itb->demapPage(vaddr, asn);
171 dtb->demapPage(vaddr, asn);
172 }
173
174 void demapInstPage(Addr vaddr, uint64_t asn)
175 {
176 itb->demapPage(vaddr, asn);
177 }
178
179 void demapDataPage(Addr vaddr, uint64_t asn)
180 {
181 dtb->demapPage(vaddr, asn);
182 }
183
184 void dumpFuncProfile();
185
186 Fault hwrei();
187
188 bool simPalCheck(int palFunc);
189
190 /*******************************************
191 * ThreadContext interface functions.
192 ******************************************/
193
194 BaseCPU *getCpuPtr() { return baseCpu; }
195
196 TheISA::TLB *getITBPtr() { return itb; }
197
198 TheISA::TLB *getDTBPtr() { return dtb; }
199
200 CheckerCPU *getCheckerCpuPtr() { return NULL; }
201
|
202 Decoder *getDecoderPtr() { return &decoder; }
| 202 TheISA::Decoder *getDecoderPtr() { return &decoder; }
|
203
204 System *getSystemPtr() { return system; }
205
206 Status status() const { return _status; }
207
208 void setStatus(Status newStatus) { _status = newStatus; }
209
210 /// Set the status to Active. Optional delay indicates number of
211 /// cycles to wait before beginning execution.
212 void activate(int delay = 1);
213
214 /// Set the status to Suspended.
215 void suspend();
216
217 /// Set the status to Halted.
218 void halt();
219
220 virtual bool misspeculating();
221
222 void copyArchRegs(ThreadContext *tc);
223
224 void clearArchRegs()
225 {
226 _pcState = 0;
227 memset(intRegs, 0, sizeof(intRegs));
228 memset(floatRegs.i, 0, sizeof(floatRegs.i));
229 isa.clear();
230 }
231
232 //
233 // New accessors for new decoder.
234 //
235 uint64_t readIntReg(int reg_idx)
236 {
237 int flatIndex = isa.flattenIntIndex(reg_idx);
238 assert(flatIndex < TheISA::NumIntRegs);
239 uint64_t regVal = intRegs[flatIndex];
240 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
241 reg_idx, flatIndex, regVal);
242 return regVal;
243 }
244
245 FloatReg readFloatReg(int reg_idx)
246 {
247 int flatIndex = isa.flattenFloatIndex(reg_idx);
248 assert(flatIndex < TheISA::NumFloatRegs);
249 FloatReg regVal = floatRegs.f[flatIndex];
250 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
251 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
252 return regVal;
253 }
254
255 FloatRegBits readFloatRegBits(int reg_idx)
256 {
257 int flatIndex = isa.flattenFloatIndex(reg_idx);
258 assert(flatIndex < TheISA::NumFloatRegs);
259 FloatRegBits regVal = floatRegs.i[flatIndex];
260 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
261 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
262 return regVal;
263 }
264
265 void setIntReg(int reg_idx, uint64_t val)
266 {
267 int flatIndex = isa.flattenIntIndex(reg_idx);
268 assert(flatIndex < TheISA::NumIntRegs);
269 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
270 reg_idx, flatIndex, val);
271 intRegs[flatIndex] = val;
272 }
273
274 void setFloatReg(int reg_idx, FloatReg val)
275 {
276 int flatIndex = isa.flattenFloatIndex(reg_idx);
277 assert(flatIndex < TheISA::NumFloatRegs);
278 floatRegs.f[flatIndex] = val;
279 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
280 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
281 }
282
283 void setFloatRegBits(int reg_idx, FloatRegBits val)
284 {
285 int flatIndex = isa.flattenFloatIndex(reg_idx);
286 assert(flatIndex < TheISA::NumFloatRegs);
287 // XXX: Fix array out of bounds compiler error for gem5.fast
288 // when checkercpu enabled
289 if (flatIndex < TheISA::NumFloatRegs)
290 floatRegs.i[flatIndex] = val;
291 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
292 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
293 }
294
295 TheISA::PCState
296 pcState()
297 {
298 return _pcState;
299 }
300
301 void
302 pcState(const TheISA::PCState &val)
303 {
304 _pcState = val;
305 }
306
307 void
308 pcStateNoRecord(const TheISA::PCState &val)
309 {
310 _pcState = val;
311 }
312
313 Addr
314 instAddr()
315 {
316 return _pcState.instAddr();
317 }
318
319 Addr
320 nextInstAddr()
321 {
322 return _pcState.nextInstAddr();
323 }
324
325 MicroPC
326 microPC()
327 {
328 return _pcState.microPC();
329 }
330
331 bool readPredicate()
332 {
333 return predicate;
334 }
335
336 void setPredicate(bool val)
337 {
338 predicate = val;
339 }
340
341 MiscReg
342 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
343 {
344 return isa.readMiscRegNoEffect(misc_reg);
345 }
346
347 MiscReg
348 readMiscReg(int misc_reg, ThreadID tid = 0)
349 {
350 return isa.readMiscReg(misc_reg, tc);
351 }
352
353 void
354 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
355 {
356 return isa.setMiscRegNoEffect(misc_reg, val);
357 }
358
359 void
360 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
361 {
362 return isa.setMiscReg(misc_reg, val, tc);
363 }
364
365 int
366 flattenIntIndex(int reg)
367 {
368 return isa.flattenIntIndex(reg);
369 }
370
371 int
372 flattenFloatIndex(int reg)
373 {
374 return isa.flattenFloatIndex(reg);
375 }
376
377 unsigned readStCondFailures() { return storeCondFailures; }
378
379 void setStCondFailures(unsigned sc_failures)
380 { storeCondFailures = sc_failures; }
381
382 void syscall(int64_t callnum)
383 {
384 process->syscall(callnum, tc);
385 }
386};
387
388
389// for non-speculative execution context, spec_mode is always false
390inline bool
391SimpleThread::misspeculating()
392{
393 return false;
394}
395
396#endif // __CPU_CPU_EXEC_CONTEXT_HH__
| 203
204 System *getSystemPtr() { return system; }
205
206 Status status() const { return _status; }
207
208 void setStatus(Status newStatus) { _status = newStatus; }
209
210 /// Set the status to Active. Optional delay indicates number of
211 /// cycles to wait before beginning execution.
212 void activate(int delay = 1);
213
214 /// Set the status to Suspended.
215 void suspend();
216
217 /// Set the status to Halted.
218 void halt();
219
220 virtual bool misspeculating();
221
222 void copyArchRegs(ThreadContext *tc);
223
224 void clearArchRegs()
225 {
226 _pcState = 0;
227 memset(intRegs, 0, sizeof(intRegs));
228 memset(floatRegs.i, 0, sizeof(floatRegs.i));
229 isa.clear();
230 }
231
232 //
233 // New accessors for new decoder.
234 //
235 uint64_t readIntReg(int reg_idx)
236 {
237 int flatIndex = isa.flattenIntIndex(reg_idx);
238 assert(flatIndex < TheISA::NumIntRegs);
239 uint64_t regVal = intRegs[flatIndex];
240 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
241 reg_idx, flatIndex, regVal);
242 return regVal;
243 }
244
245 FloatReg readFloatReg(int reg_idx)
246 {
247 int flatIndex = isa.flattenFloatIndex(reg_idx);
248 assert(flatIndex < TheISA::NumFloatRegs);
249 FloatReg regVal = floatRegs.f[flatIndex];
250 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
251 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
252 return regVal;
253 }
254
255 FloatRegBits readFloatRegBits(int reg_idx)
256 {
257 int flatIndex = isa.flattenFloatIndex(reg_idx);
258 assert(flatIndex < TheISA::NumFloatRegs);
259 FloatRegBits regVal = floatRegs.i[flatIndex];
260 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
261 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
262 return regVal;
263 }
264
265 void setIntReg(int reg_idx, uint64_t val)
266 {
267 int flatIndex = isa.flattenIntIndex(reg_idx);
268 assert(flatIndex < TheISA::NumIntRegs);
269 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
270 reg_idx, flatIndex, val);
271 intRegs[flatIndex] = val;
272 }
273
274 void setFloatReg(int reg_idx, FloatReg val)
275 {
276 int flatIndex = isa.flattenFloatIndex(reg_idx);
277 assert(flatIndex < TheISA::NumFloatRegs);
278 floatRegs.f[flatIndex] = val;
279 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
280 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
281 }
282
283 void setFloatRegBits(int reg_idx, FloatRegBits val)
284 {
285 int flatIndex = isa.flattenFloatIndex(reg_idx);
286 assert(flatIndex < TheISA::NumFloatRegs);
287 // XXX: Fix array out of bounds compiler error for gem5.fast
288 // when checkercpu enabled
289 if (flatIndex < TheISA::NumFloatRegs)
290 floatRegs.i[flatIndex] = val;
291 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
292 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
293 }
294
295 TheISA::PCState
296 pcState()
297 {
298 return _pcState;
299 }
300
301 void
302 pcState(const TheISA::PCState &val)
303 {
304 _pcState = val;
305 }
306
307 void
308 pcStateNoRecord(const TheISA::PCState &val)
309 {
310 _pcState = val;
311 }
312
313 Addr
314 instAddr()
315 {
316 return _pcState.instAddr();
317 }
318
319 Addr
320 nextInstAddr()
321 {
322 return _pcState.nextInstAddr();
323 }
324
325 MicroPC
326 microPC()
327 {
328 return _pcState.microPC();
329 }
330
331 bool readPredicate()
332 {
333 return predicate;
334 }
335
336 void setPredicate(bool val)
337 {
338 predicate = val;
339 }
340
341 MiscReg
342 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
343 {
344 return isa.readMiscRegNoEffect(misc_reg);
345 }
346
347 MiscReg
348 readMiscReg(int misc_reg, ThreadID tid = 0)
349 {
350 return isa.readMiscReg(misc_reg, tc);
351 }
352
353 void
354 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
355 {
356 return isa.setMiscRegNoEffect(misc_reg, val);
357 }
358
359 void
360 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
361 {
362 return isa.setMiscReg(misc_reg, val, tc);
363 }
364
365 int
366 flattenIntIndex(int reg)
367 {
368 return isa.flattenIntIndex(reg);
369 }
370
371 int
372 flattenFloatIndex(int reg)
373 {
374 return isa.flattenFloatIndex(reg);
375 }
376
377 unsigned readStCondFailures() { return storeCondFailures; }
378
379 void setStCondFailures(unsigned sc_failures)
380 { storeCondFailures = sc_failures; }
381
382 void syscall(int64_t callnum)
383 {
384 process->syscall(callnum, tc);
385 }
386};
387
388
389// for non-speculative execution context, spec_mode is always false
390inline bool
391SimpleThread::misspeculating()
392{
393 return false;
394}
395
396#endif // __CPU_CPU_EXEC_CONTEXT_HH__
|