1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa.hh"
36#include "arch/isa_traits.hh"
37#include "arch/registers.hh"
38#include "arch/tlb.hh"
39#include "arch/types.hh"
40#include "base/types.hh"
41#include "config/full_system.hh"
42#include "config/the_isa.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/thread_state.hh"
45#include "mem/request.hh"
46#include "sim/byteswap.hh"
47#include "sim/eventq.hh"
48#include "sim/serialize.hh"
49
50class BaseCPU;
51
52#if FULL_SYSTEM
53
54#include "sim/system.hh"
55
56class FunctionProfile;
57class ProfileNode;
58class FunctionalPort;
59class PhysicalPort;
60
61namespace TheISA {
62 namespace Kernel {
63 class Statistics;
64 };
65};
66
67#else // !FULL_SYSTEM
68
69#include "sim/process.hh"
70#include "mem/page_table.hh"
71class TranslatingPort;
72
73#endif // FULL_SYSTEM
74
75/**
76 * The SimpleThread object provides a combination of the ThreadState
77 * object and the ThreadContext interface. It implements the
78 * ThreadContext interface so that a ProxyThreadContext class can be
79 * made using SimpleThread as the template parameter (see
80 * thread_context.hh). It adds to the ThreadState object by adding all
81 * the objects needed for simple functional execution, including a
82 * simple architectural register file, and pointers to the ITB and DTB
83 * in full system mode. For CPU models that do not need more advanced
84 * ways to hold state (i.e. a separate physical register file, or
85 * separate fetch and commit PC's), this SimpleThread class provides
86 * all the necessary state for full architecture-level functional
87 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
88 * examples.
89 */
90
91class SimpleThread : public ThreadState
92{
93 protected:
94 typedef TheISA::MachInst MachInst;
95 typedef TheISA::MiscReg MiscReg;
96 typedef TheISA::FloatReg FloatReg;
97 typedef TheISA::FloatRegBits FloatRegBits;
98 public:
99 typedef ThreadContext::Status Status;
100
101 protected:
102 union {
103 FloatReg f[TheISA::NumFloatRegs];
104 FloatRegBits i[TheISA::NumFloatRegs];
105 } floatRegs;
106 TheISA::IntReg intRegs[TheISA::NumIntRegs];
107 TheISA::ISA isa; // one "instance" of the current ISA.
108
109 /** The current microcode pc for the currently executing macro
110 * operation.
111 */
112 MicroPC microPC;
113
114 /** The next microcode pc for the currently executing macro
115 * operation.
116 */
117 MicroPC nextMicroPC;
118
119 /** The current pc.
120 */
121 Addr PC;
122
123 /** The next pc.
124 */
125 Addr nextPC;
126
127 /** The next next pc.
128 */
129 Addr nextNPC;
130
| 1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa.hh"
36#include "arch/isa_traits.hh"
37#include "arch/registers.hh"
38#include "arch/tlb.hh"
39#include "arch/types.hh"
40#include "base/types.hh"
41#include "config/full_system.hh"
42#include "config/the_isa.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/thread_state.hh"
45#include "mem/request.hh"
46#include "sim/byteswap.hh"
47#include "sim/eventq.hh"
48#include "sim/serialize.hh"
49
50class BaseCPU;
51
52#if FULL_SYSTEM
53
54#include "sim/system.hh"
55
56class FunctionProfile;
57class ProfileNode;
58class FunctionalPort;
59class PhysicalPort;
60
61namespace TheISA {
62 namespace Kernel {
63 class Statistics;
64 };
65};
66
67#else // !FULL_SYSTEM
68
69#include "sim/process.hh"
70#include "mem/page_table.hh"
71class TranslatingPort;
72
73#endif // FULL_SYSTEM
74
75/**
76 * The SimpleThread object provides a combination of the ThreadState
77 * object and the ThreadContext interface. It implements the
78 * ThreadContext interface so that a ProxyThreadContext class can be
79 * made using SimpleThread as the template parameter (see
80 * thread_context.hh). It adds to the ThreadState object by adding all
81 * the objects needed for simple functional execution, including a
82 * simple architectural register file, and pointers to the ITB and DTB
83 * in full system mode. For CPU models that do not need more advanced
84 * ways to hold state (i.e. a separate physical register file, or
85 * separate fetch and commit PC's), this SimpleThread class provides
86 * all the necessary state for full architecture-level functional
87 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
88 * examples.
89 */
90
91class SimpleThread : public ThreadState
92{
93 protected:
94 typedef TheISA::MachInst MachInst;
95 typedef TheISA::MiscReg MiscReg;
96 typedef TheISA::FloatReg FloatReg;
97 typedef TheISA::FloatRegBits FloatRegBits;
98 public:
99 typedef ThreadContext::Status Status;
100
101 protected:
102 union {
103 FloatReg f[TheISA::NumFloatRegs];
104 FloatRegBits i[TheISA::NumFloatRegs];
105 } floatRegs;
106 TheISA::IntReg intRegs[TheISA::NumIntRegs];
107 TheISA::ISA isa; // one "instance" of the current ISA.
108
109 /** The current microcode pc for the currently executing macro
110 * operation.
111 */
112 MicroPC microPC;
113
114 /** The next microcode pc for the currently executing macro
115 * operation.
116 */
117 MicroPC nextMicroPC;
118
119 /** The current pc.
120 */
121 Addr PC;
122
123 /** The next pc.
124 */
125 Addr nextPC;
126
127 /** The next next pc.
128 */
129 Addr nextNPC;
130
|
131 public:
132 // pointer to CPU associated with this SimpleThread
133 BaseCPU *cpu;
134
135 ProxyThreadContext<SimpleThread> *tc;
136
137 System *system;
138
139 TheISA::TLB *itb;
140 TheISA::TLB *dtb;
141
142 // constructor: initialize SimpleThread from given process structure
143#if FULL_SYSTEM
144 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
145 TheISA::TLB *_itb, TheISA::TLB *_dtb,
146 bool use_kernel_stats = true);
147#else
148 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
149 TheISA::TLB *_itb, TheISA::TLB *_dtb);
150#endif
151
152 SimpleThread();
153
154 virtual ~SimpleThread();
155
156 virtual void takeOverFrom(ThreadContext *oldContext);
157
158 void regStats(const std::string &name);
159
160 void copyTC(ThreadContext *context);
161
162 void copyState(ThreadContext *oldContext);
163
164 void serialize(std::ostream &os);
165 void unserialize(Checkpoint *cp, const std::string §ion);
166
167 /***************************************************************
168 * SimpleThread functions to provide CPU with access to various
169 * state.
170 **************************************************************/
171
172 /** Returns the pointer to this SimpleThread's ThreadContext. Used
173 * when a ThreadContext must be passed to objects outside of the
174 * CPU.
175 */
176 ThreadContext *getTC() { return tc; }
177
178 void demapPage(Addr vaddr, uint64_t asn)
179 {
180 itb->demapPage(vaddr, asn);
181 dtb->demapPage(vaddr, asn);
182 }
183
184 void demapInstPage(Addr vaddr, uint64_t asn)
185 {
186 itb->demapPage(vaddr, asn);
187 }
188
189 void demapDataPage(Addr vaddr, uint64_t asn)
190 {
191 dtb->demapPage(vaddr, asn);
192 }
193
194#if FULL_SYSTEM
195 void dumpFuncProfile();
196
197 Fault hwrei();
198
199 bool simPalCheck(int palFunc);
200
201#endif
202
203 /*******************************************
204 * ThreadContext interface functions.
205 ******************************************/
206
207 BaseCPU *getCpuPtr() { return cpu; }
208
209 TheISA::TLB *getITBPtr() { return itb; }
210
211 TheISA::TLB *getDTBPtr() { return dtb; }
212
213 System *getSystemPtr() { return system; }
214
215#if FULL_SYSTEM
216 FunctionalPort *getPhysPort() { return physPort; }
217
218 /** Return a virtual port. This port cannot be cached locally in an object.
219 * After a CPU switch it may point to the wrong memory object which could
220 * mean stale data.
221 */
222 VirtualPort *getVirtPort() { return virtPort; }
223#endif
224
225 Status status() const { return _status; }
226
227 void setStatus(Status newStatus) { _status = newStatus; }
228
229 /// Set the status to Active. Optional delay indicates number of
230 /// cycles to wait before beginning execution.
231 void activate(int delay = 1);
232
233 /// Set the status to Suspended.
234 void suspend();
235
236 /// Set the status to Halted.
237 void halt();
238
239 virtual bool misspeculating();
240
241 Fault instRead(RequestPtr &req)
242 {
243 panic("instRead not implemented");
244 // return funcPhysMem->read(req, inst);
245 return NoFault;
246 }
247
248 void copyArchRegs(ThreadContext *tc);
249
250 void clearArchRegs()
251 {
252 microPC = 0;
253 nextMicroPC = 1;
254 PC = nextPC = nextNPC = 0;
255 memset(intRegs, 0, sizeof(intRegs));
256 memset(floatRegs.i, 0, sizeof(floatRegs.i));
257 isa.clear();
258 }
259
260 //
261 // New accessors for new decoder.
262 //
263 uint64_t readIntReg(int reg_idx)
264 {
265 int flatIndex = isa.flattenIntIndex(reg_idx);
266 assert(flatIndex < TheISA::NumIntRegs);
267 uint64_t regVal = intRegs[flatIndex];
268 DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", reg_idx, regVal);
269 return regVal;
270 }
271
272 FloatReg readFloatReg(int reg_idx)
273 {
274 int flatIndex = isa.flattenFloatIndex(reg_idx);
275 assert(flatIndex < TheISA::NumFloatRegs);
276 FloatReg regVal = floatRegs.f[flatIndex];
277 DPRINTF(FloatRegs, "Reading float reg %d as %f, %#x.\n",
278 reg_idx, regVal, floatRegs.i[flatIndex]);
279 return regVal;
280 }
281
282 FloatRegBits readFloatRegBits(int reg_idx)
283 {
284 int flatIndex = isa.flattenFloatIndex(reg_idx);
285 assert(flatIndex < TheISA::NumFloatRegs);
286 FloatRegBits regVal = floatRegs.i[flatIndex];
287 DPRINTF(FloatRegs, "Reading float reg %d bits as %#x, %f.\n",
288 reg_idx, regVal, floatRegs.f[flatIndex]);
289 return regVal;
290 }
291
292 void setIntReg(int reg_idx, uint64_t val)
293 {
294 int flatIndex = isa.flattenIntIndex(reg_idx);
295 assert(flatIndex < TheISA::NumIntRegs);
296 DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", reg_idx, val);
297 intRegs[flatIndex] = val;
298 }
299
300 void setFloatReg(int reg_idx, FloatReg val)
301 {
302 int flatIndex = isa.flattenFloatIndex(reg_idx);
303 assert(flatIndex < TheISA::NumFloatRegs);
304 floatRegs.f[flatIndex] = val;
305 DPRINTF(FloatRegs, "Setting float reg %d to %f, %#x.\n",
306 reg_idx, val, floatRegs.i[flatIndex]);
307 }
308
309 void setFloatRegBits(int reg_idx, FloatRegBits val)
310 {
311 int flatIndex = isa.flattenFloatIndex(reg_idx);
312 assert(flatIndex < TheISA::NumFloatRegs);
313 floatRegs.i[flatIndex] = val;
314 DPRINTF(FloatRegs, "Setting float reg %d bits to %#x, %#f.\n",
315 reg_idx, val, floatRegs.f[flatIndex]);
316 }
317
318 uint64_t readPC()
319 {
320 return PC;
321 }
322
323 void setPC(uint64_t val)
324 {
325 PC = val;
326 }
327
328 uint64_t readMicroPC()
329 {
330 return microPC;
331 }
332
333 void setMicroPC(uint64_t val)
334 {
335 microPC = val;
336 }
337
338 uint64_t readNextPC()
339 {
340 return nextPC;
341 }
342
343 void setNextPC(uint64_t val)
344 {
345 nextPC = val;
346 }
347
348 uint64_t readNextMicroPC()
349 {
350 return nextMicroPC;
351 }
352
353 void setNextMicroPC(uint64_t val)
354 {
355 nextMicroPC = val;
356 }
357
358 uint64_t readNextNPC()
359 {
360#if ISA_HAS_DELAY_SLOT
361 return nextNPC;
362#else
363 return nextPC + sizeof(TheISA::MachInst);
364#endif
365 }
366
367 void setNextNPC(uint64_t val)
368 {
369#if ISA_HAS_DELAY_SLOT
370 nextNPC = val;
371#endif
372 }
373
| 134 public:
135 // pointer to CPU associated with this SimpleThread
136 BaseCPU *cpu;
137
138 ProxyThreadContext<SimpleThread> *tc;
139
140 System *system;
141
142 TheISA::TLB *itb;
143 TheISA::TLB *dtb;
144
145 // constructor: initialize SimpleThread from given process structure
146#if FULL_SYSTEM
147 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
148 TheISA::TLB *_itb, TheISA::TLB *_dtb,
149 bool use_kernel_stats = true);
150#else
151 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
152 TheISA::TLB *_itb, TheISA::TLB *_dtb);
153#endif
154
155 SimpleThread();
156
157 virtual ~SimpleThread();
158
159 virtual void takeOverFrom(ThreadContext *oldContext);
160
161 void regStats(const std::string &name);
162
163 void copyTC(ThreadContext *context);
164
165 void copyState(ThreadContext *oldContext);
166
167 void serialize(std::ostream &os);
168 void unserialize(Checkpoint *cp, const std::string §ion);
169
170 /***************************************************************
171 * SimpleThread functions to provide CPU with access to various
172 * state.
173 **************************************************************/
174
175 /** Returns the pointer to this SimpleThread's ThreadContext. Used
176 * when a ThreadContext must be passed to objects outside of the
177 * CPU.
178 */
179 ThreadContext *getTC() { return tc; }
180
181 void demapPage(Addr vaddr, uint64_t asn)
182 {
183 itb->demapPage(vaddr, asn);
184 dtb->demapPage(vaddr, asn);
185 }
186
187 void demapInstPage(Addr vaddr, uint64_t asn)
188 {
189 itb->demapPage(vaddr, asn);
190 }
191
192 void demapDataPage(Addr vaddr, uint64_t asn)
193 {
194 dtb->demapPage(vaddr, asn);
195 }
196
197#if FULL_SYSTEM
198 void dumpFuncProfile();
199
200 Fault hwrei();
201
202 bool simPalCheck(int palFunc);
203
204#endif
205
206 /*******************************************
207 * ThreadContext interface functions.
208 ******************************************/
209
210 BaseCPU *getCpuPtr() { return cpu; }
211
212 TheISA::TLB *getITBPtr() { return itb; }
213
214 TheISA::TLB *getDTBPtr() { return dtb; }
215
216 System *getSystemPtr() { return system; }
217
218#if FULL_SYSTEM
219 FunctionalPort *getPhysPort() { return physPort; }
220
221 /** Return a virtual port. This port cannot be cached locally in an object.
222 * After a CPU switch it may point to the wrong memory object which could
223 * mean stale data.
224 */
225 VirtualPort *getVirtPort() { return virtPort; }
226#endif
227
228 Status status() const { return _status; }
229
230 void setStatus(Status newStatus) { _status = newStatus; }
231
232 /// Set the status to Active. Optional delay indicates number of
233 /// cycles to wait before beginning execution.
234 void activate(int delay = 1);
235
236 /// Set the status to Suspended.
237 void suspend();
238
239 /// Set the status to Halted.
240 void halt();
241
242 virtual bool misspeculating();
243
244 Fault instRead(RequestPtr &req)
245 {
246 panic("instRead not implemented");
247 // return funcPhysMem->read(req, inst);
248 return NoFault;
249 }
250
251 void copyArchRegs(ThreadContext *tc);
252
253 void clearArchRegs()
254 {
255 microPC = 0;
256 nextMicroPC = 1;
257 PC = nextPC = nextNPC = 0;
258 memset(intRegs, 0, sizeof(intRegs));
259 memset(floatRegs.i, 0, sizeof(floatRegs.i));
260 isa.clear();
261 }
262
263 //
264 // New accessors for new decoder.
265 //
266 uint64_t readIntReg(int reg_idx)
267 {
268 int flatIndex = isa.flattenIntIndex(reg_idx);
269 assert(flatIndex < TheISA::NumIntRegs);
270 uint64_t regVal = intRegs[flatIndex];
271 DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", reg_idx, regVal);
272 return regVal;
273 }
274
275 FloatReg readFloatReg(int reg_idx)
276 {
277 int flatIndex = isa.flattenFloatIndex(reg_idx);
278 assert(flatIndex < TheISA::NumFloatRegs);
279 FloatReg regVal = floatRegs.f[flatIndex];
280 DPRINTF(FloatRegs, "Reading float reg %d as %f, %#x.\n",
281 reg_idx, regVal, floatRegs.i[flatIndex]);
282 return regVal;
283 }
284
285 FloatRegBits readFloatRegBits(int reg_idx)
286 {
287 int flatIndex = isa.flattenFloatIndex(reg_idx);
288 assert(flatIndex < TheISA::NumFloatRegs);
289 FloatRegBits regVal = floatRegs.i[flatIndex];
290 DPRINTF(FloatRegs, "Reading float reg %d bits as %#x, %f.\n",
291 reg_idx, regVal, floatRegs.f[flatIndex]);
292 return regVal;
293 }
294
295 void setIntReg(int reg_idx, uint64_t val)
296 {
297 int flatIndex = isa.flattenIntIndex(reg_idx);
298 assert(flatIndex < TheISA::NumIntRegs);
299 DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", reg_idx, val);
300 intRegs[flatIndex] = val;
301 }
302
303 void setFloatReg(int reg_idx, FloatReg val)
304 {
305 int flatIndex = isa.flattenFloatIndex(reg_idx);
306 assert(flatIndex < TheISA::NumFloatRegs);
307 floatRegs.f[flatIndex] = val;
308 DPRINTF(FloatRegs, "Setting float reg %d to %f, %#x.\n",
309 reg_idx, val, floatRegs.i[flatIndex]);
310 }
311
312 void setFloatRegBits(int reg_idx, FloatRegBits val)
313 {
314 int flatIndex = isa.flattenFloatIndex(reg_idx);
315 assert(flatIndex < TheISA::NumFloatRegs);
316 floatRegs.i[flatIndex] = val;
317 DPRINTF(FloatRegs, "Setting float reg %d bits to %#x, %#f.\n",
318 reg_idx, val, floatRegs.f[flatIndex]);
319 }
320
321 uint64_t readPC()
322 {
323 return PC;
324 }
325
326 void setPC(uint64_t val)
327 {
328 PC = val;
329 }
330
331 uint64_t readMicroPC()
332 {
333 return microPC;
334 }
335
336 void setMicroPC(uint64_t val)
337 {
338 microPC = val;
339 }
340
341 uint64_t readNextPC()
342 {
343 return nextPC;
344 }
345
346 void setNextPC(uint64_t val)
347 {
348 nextPC = val;
349 }
350
351 uint64_t readNextMicroPC()
352 {
353 return nextMicroPC;
354 }
355
356 void setNextMicroPC(uint64_t val)
357 {
358 nextMicroPC = val;
359 }
360
361 uint64_t readNextNPC()
362 {
363#if ISA_HAS_DELAY_SLOT
364 return nextNPC;
365#else
366 return nextPC + sizeof(TheISA::MachInst);
367#endif
368 }
369
370 void setNextNPC(uint64_t val)
371 {
372#if ISA_HAS_DELAY_SLOT
373 nextNPC = val;
374#endif
375 }
376
|
374 MiscReg
375 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
376 {
377 return isa.readMiscRegNoEffect(misc_reg);
378 }
379
380 MiscReg
381 readMiscReg(int misc_reg, ThreadID tid = 0)
382 {
383 return isa.readMiscReg(misc_reg, tc);
384 }
385
386 void
387 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
388 {
389 return isa.setMiscRegNoEffect(misc_reg, val);
390 }
391
392 void
393 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
394 {
395 return isa.setMiscReg(misc_reg, val, tc);
396 }
397
398 int
399 flattenIntIndex(int reg)
400 {
401 return isa.flattenIntIndex(reg);
402 }
403
404 int
405 flattenFloatIndex(int reg)
406 {
407 return isa.flattenFloatIndex(reg);
408 }
409
410 unsigned readStCondFailures() { return storeCondFailures; }
411
412 void setStCondFailures(unsigned sc_failures)
413 { storeCondFailures = sc_failures; }
414
415#if !FULL_SYSTEM
416 void syscall(int64_t callnum)
417 {
418 process->syscall(callnum, tc);
419 }
420#endif
421};
422
423
424// for non-speculative execution context, spec_mode is always false
425inline bool
426SimpleThread::misspeculating()
427{
428 return false;
429}
430
431#endif // __CPU_CPU_EXEC_CONTEXT_HH__
| 387 MiscReg
388 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
389 {
390 return isa.readMiscRegNoEffect(misc_reg);
391 }
392
393 MiscReg
394 readMiscReg(int misc_reg, ThreadID tid = 0)
395 {
396 return isa.readMiscReg(misc_reg, tc);
397 }
398
399 void
400 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
401 {
402 return isa.setMiscRegNoEffect(misc_reg, val);
403 }
404
405 void
406 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
407 {
408 return isa.setMiscReg(misc_reg, val, tc);
409 }
410
411 int
412 flattenIntIndex(int reg)
413 {
414 return isa.flattenIntIndex(reg);
415 }
416
417 int
418 flattenFloatIndex(int reg)
419 {
420 return isa.flattenFloatIndex(reg);
421 }
422
423 unsigned readStCondFailures() { return storeCondFailures; }
424
425 void setStCondFailures(unsigned sc_failures)
426 { storeCondFailures = sc_failures; }
427
428#if !FULL_SYSTEM
429 void syscall(int64_t callnum)
430 {
431 process->syscall(callnum, tc);
432 }
433#endif
434};
435
436
437// for non-speculative execution context, spec_mode is always false
438inline bool
439SimpleThread::misspeculating()
440{
441 return false;
442}
443
444#endif // __CPU_CPU_EXEC_CONTEXT_HH__
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