1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa.hh"
36#include "arch/isa_traits.hh"
37#include "arch/regfile.hh"
38#include "arch/tlb.hh"
39#include "base/types.hh"
40#include "config/full_system.hh"
41#include "cpu/thread_context.hh"
42#include "cpu/thread_state.hh"
43#include "mem/request.hh"
44#include "sim/byteswap.hh"
45#include "sim/eventq.hh"
46#include "sim/serialize.hh"
47
48class BaseCPU;
49
50#if FULL_SYSTEM
51
52#include "sim/system.hh"
53
54class FunctionProfile;
55class ProfileNode;
56class FunctionalPort;
57class PhysicalPort;
58
59namespace TheISA {
60 namespace Kernel {
61 class Statistics;
62 };
63};
64
65#else // !FULL_SYSTEM
66
67#include "sim/process.hh"
68#include "mem/page_table.hh"
69class TranslatingPort;
70
71#endif // FULL_SYSTEM
72
73/**
74 * The SimpleThread object provides a combination of the ThreadState
75 * object and the ThreadContext interface. It implements the
76 * ThreadContext interface so that a ProxyThreadContext class can be
77 * made using SimpleThread as the template parameter (see
78 * thread_context.hh). It adds to the ThreadState object by adding all
79 * the objects needed for simple functional execution, including a
80 * simple architectural register file, and pointers to the ITB and DTB
81 * in full system mode. For CPU models that do not need more advanced
82 * ways to hold state (i.e. a separate physical register file, or
83 * separate fetch and commit PC's), this SimpleThread class provides
84 * all the necessary state for full architecture-level functional
85 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
86 * examples.
87 */
88
89class SimpleThread : public ThreadState
90{
91 protected:
92 typedef TheISA::RegFile RegFile;
93 typedef TheISA::MachInst MachInst;
94 typedef TheISA::MiscReg MiscReg;
95 typedef TheISA::FloatReg FloatReg;
96 typedef TheISA::FloatRegBits FloatRegBits;
97 public:
98 typedef ThreadContext::Status Status;
99
100 protected:
101 RegFile regs; // correct-path register context
| 1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa.hh"
36#include "arch/isa_traits.hh"
37#include "arch/regfile.hh"
38#include "arch/tlb.hh"
39#include "base/types.hh"
40#include "config/full_system.hh"
41#include "cpu/thread_context.hh"
42#include "cpu/thread_state.hh"
43#include "mem/request.hh"
44#include "sim/byteswap.hh"
45#include "sim/eventq.hh"
46#include "sim/serialize.hh"
47
48class BaseCPU;
49
50#if FULL_SYSTEM
51
52#include "sim/system.hh"
53
54class FunctionProfile;
55class ProfileNode;
56class FunctionalPort;
57class PhysicalPort;
58
59namespace TheISA {
60 namespace Kernel {
61 class Statistics;
62 };
63};
64
65#else // !FULL_SYSTEM
66
67#include "sim/process.hh"
68#include "mem/page_table.hh"
69class TranslatingPort;
70
71#endif // FULL_SYSTEM
72
73/**
74 * The SimpleThread object provides a combination of the ThreadState
75 * object and the ThreadContext interface. It implements the
76 * ThreadContext interface so that a ProxyThreadContext class can be
77 * made using SimpleThread as the template parameter (see
78 * thread_context.hh). It adds to the ThreadState object by adding all
79 * the objects needed for simple functional execution, including a
80 * simple architectural register file, and pointers to the ITB and DTB
81 * in full system mode. For CPU models that do not need more advanced
82 * ways to hold state (i.e. a separate physical register file, or
83 * separate fetch and commit PC's), this SimpleThread class provides
84 * all the necessary state for full architecture-level functional
85 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
86 * examples.
87 */
88
89class SimpleThread : public ThreadState
90{
91 protected:
92 typedef TheISA::RegFile RegFile;
93 typedef TheISA::MachInst MachInst;
94 typedef TheISA::MiscReg MiscReg;
95 typedef TheISA::FloatReg FloatReg;
96 typedef TheISA::FloatRegBits FloatRegBits;
97 public:
98 typedef ThreadContext::Status Status;
99
100 protected:
101 RegFile regs; // correct-path register context
|
| 102 union {
103 FloatReg f[TheISA::NumFloatRegs];
104 FloatRegBits i[TheISA::NumFloatRegs];
105 } floatRegs;
|
102 TheISA::ISA isa; // one "instance" of the current ISA.
103
104 public:
105 // pointer to CPU associated with this SimpleThread
106 BaseCPU *cpu;
107
108 ProxyThreadContext<SimpleThread> *tc;
109
110 System *system;
111
112 TheISA::TLB *itb;
113 TheISA::TLB *dtb;
114
115 // constructor: initialize SimpleThread from given process structure
116#if FULL_SYSTEM
117 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
118 TheISA::TLB *_itb, TheISA::TLB *_dtb,
119 bool use_kernel_stats = true);
120#else
121 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
122 TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid);
123#endif
124
125 SimpleThread();
126
127 virtual ~SimpleThread();
128
129 virtual void takeOverFrom(ThreadContext *oldContext);
130
131 void regStats(const std::string &name);
132
133 void copyTC(ThreadContext *context);
134
135 void copyState(ThreadContext *oldContext);
136
137 void serialize(std::ostream &os);
138 void unserialize(Checkpoint *cp, const std::string §ion);
139
140 /***************************************************************
141 * SimpleThread functions to provide CPU with access to various
142 * state.
143 **************************************************************/
144
145 /** Returns the pointer to this SimpleThread's ThreadContext. Used
146 * when a ThreadContext must be passed to objects outside of the
147 * CPU.
148 */
149 ThreadContext *getTC() { return tc; }
150
151 void demapPage(Addr vaddr, uint64_t asn)
152 {
153 itb->demapPage(vaddr, asn);
154 dtb->demapPage(vaddr, asn);
155 }
156
157 void demapInstPage(Addr vaddr, uint64_t asn)
158 {
159 itb->demapPage(vaddr, asn);
160 }
161
162 void demapDataPage(Addr vaddr, uint64_t asn)
163 {
164 dtb->demapPage(vaddr, asn);
165 }
166
167#if FULL_SYSTEM
168 int getInstAsid() { return isa.instAsid(); }
169 int getDataAsid() { return isa.dataAsid(); }
170
171 void dumpFuncProfile();
172
173 Fault hwrei();
174
175 bool simPalCheck(int palFunc);
176
177#endif
178
179 /*******************************************
180 * ThreadContext interface functions.
181 ******************************************/
182
183 BaseCPU *getCpuPtr() { return cpu; }
184
185 TheISA::TLB *getITBPtr() { return itb; }
186
187 TheISA::TLB *getDTBPtr() { return dtb; }
188
189 System *getSystemPtr() { return system; }
190
191#if FULL_SYSTEM
192 FunctionalPort *getPhysPort() { return physPort; }
193
194 /** Return a virtual port. This port cannot be cached locally in an object.
195 * After a CPU switch it may point to the wrong memory object which could
196 * mean stale data.
197 */
198 VirtualPort *getVirtPort() { return virtPort; }
199#endif
200
201 Status status() const { return _status; }
202
203 void setStatus(Status newStatus) { _status = newStatus; }
204
205 /// Set the status to Active. Optional delay indicates number of
206 /// cycles to wait before beginning execution.
207 void activate(int delay = 1);
208
209 /// Set the status to Suspended.
210 void suspend();
211
212 /// Set the status to Halted.
213 void halt();
214
215 virtual bool misspeculating();
216
217 Fault instRead(RequestPtr &req)
218 {
219 panic("instRead not implemented");
220 // return funcPhysMem->read(req, inst);
221 return NoFault;
222 }
223
224 void copyArchRegs(ThreadContext *tc);
225
| 106 TheISA::ISA isa; // one "instance" of the current ISA.
107
108 public:
109 // pointer to CPU associated with this SimpleThread
110 BaseCPU *cpu;
111
112 ProxyThreadContext<SimpleThread> *tc;
113
114 System *system;
115
116 TheISA::TLB *itb;
117 TheISA::TLB *dtb;
118
119 // constructor: initialize SimpleThread from given process structure
120#if FULL_SYSTEM
121 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
122 TheISA::TLB *_itb, TheISA::TLB *_dtb,
123 bool use_kernel_stats = true);
124#else
125 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
126 TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid);
127#endif
128
129 SimpleThread();
130
131 virtual ~SimpleThread();
132
133 virtual void takeOverFrom(ThreadContext *oldContext);
134
135 void regStats(const std::string &name);
136
137 void copyTC(ThreadContext *context);
138
139 void copyState(ThreadContext *oldContext);
140
141 void serialize(std::ostream &os);
142 void unserialize(Checkpoint *cp, const std::string §ion);
143
144 /***************************************************************
145 * SimpleThread functions to provide CPU with access to various
146 * state.
147 **************************************************************/
148
149 /** Returns the pointer to this SimpleThread's ThreadContext. Used
150 * when a ThreadContext must be passed to objects outside of the
151 * CPU.
152 */
153 ThreadContext *getTC() { return tc; }
154
155 void demapPage(Addr vaddr, uint64_t asn)
156 {
157 itb->demapPage(vaddr, asn);
158 dtb->demapPage(vaddr, asn);
159 }
160
161 void demapInstPage(Addr vaddr, uint64_t asn)
162 {
163 itb->demapPage(vaddr, asn);
164 }
165
166 void demapDataPage(Addr vaddr, uint64_t asn)
167 {
168 dtb->demapPage(vaddr, asn);
169 }
170
171#if FULL_SYSTEM
172 int getInstAsid() { return isa.instAsid(); }
173 int getDataAsid() { return isa.dataAsid(); }
174
175 void dumpFuncProfile();
176
177 Fault hwrei();
178
179 bool simPalCheck(int palFunc);
180
181#endif
182
183 /*******************************************
184 * ThreadContext interface functions.
185 ******************************************/
186
187 BaseCPU *getCpuPtr() { return cpu; }
188
189 TheISA::TLB *getITBPtr() { return itb; }
190
191 TheISA::TLB *getDTBPtr() { return dtb; }
192
193 System *getSystemPtr() { return system; }
194
195#if FULL_SYSTEM
196 FunctionalPort *getPhysPort() { return physPort; }
197
198 /** Return a virtual port. This port cannot be cached locally in an object.
199 * After a CPU switch it may point to the wrong memory object which could
200 * mean stale data.
201 */
202 VirtualPort *getVirtPort() { return virtPort; }
203#endif
204
205 Status status() const { return _status; }
206
207 void setStatus(Status newStatus) { _status = newStatus; }
208
209 /// Set the status to Active. Optional delay indicates number of
210 /// cycles to wait before beginning execution.
211 void activate(int delay = 1);
212
213 /// Set the status to Suspended.
214 void suspend();
215
216 /// Set the status to Halted.
217 void halt();
218
219 virtual bool misspeculating();
220
221 Fault instRead(RequestPtr &req)
222 {
223 panic("instRead not implemented");
224 // return funcPhysMem->read(req, inst);
225 return NoFault;
226 }
227
228 void copyArchRegs(ThreadContext *tc);
229
|
226 void clearArchRegs() { regs.clear(); }
| 230 void clearArchRegs()
231 {
232 regs.clear();
233 memset(floatRegs.i, 0, sizeof(floatRegs.i));
234 }
|
227
228 //
229 // New accessors for new decoder.
230 //
231 uint64_t readIntReg(int reg_idx)
232 {
233 int flatIndex = isa.flattenIntIndex(reg_idx);
234 return regs.readIntReg(flatIndex);
235 }
236
237 FloatReg readFloatReg(int reg_idx)
238 {
239 int flatIndex = isa.flattenFloatIndex(reg_idx);
| 235
236 //
237 // New accessors for new decoder.
238 //
239 uint64_t readIntReg(int reg_idx)
240 {
241 int flatIndex = isa.flattenIntIndex(reg_idx);
242 return regs.readIntReg(flatIndex);
243 }
244
245 FloatReg readFloatReg(int reg_idx)
246 {
247 int flatIndex = isa.flattenFloatIndex(reg_idx);
|
240 return regs.readFloatReg(flatIndex);
| 248 return floatRegs.f[flatIndex];
|
241 }
242
243 FloatRegBits readFloatRegBits(int reg_idx)
244 {
245 int flatIndex = isa.flattenFloatIndex(reg_idx);
| 249 }
250
251 FloatRegBits readFloatRegBits(int reg_idx)
252 {
253 int flatIndex = isa.flattenFloatIndex(reg_idx);
|
246 return regs.readFloatRegBits(flatIndex);
| 254 return floatRegs.i[flatIndex];
|
247 }
248
249 void setIntReg(int reg_idx, uint64_t val)
250 {
251 int flatIndex = isa.flattenIntIndex(reg_idx);
252 regs.setIntReg(flatIndex, val);
253 }
254
255 void setFloatReg(int reg_idx, FloatReg val)
256 {
257 int flatIndex = isa.flattenFloatIndex(reg_idx);
| 255 }
256
257 void setIntReg(int reg_idx, uint64_t val)
258 {
259 int flatIndex = isa.flattenIntIndex(reg_idx);
260 regs.setIntReg(flatIndex, val);
261 }
262
263 void setFloatReg(int reg_idx, FloatReg val)
264 {
265 int flatIndex = isa.flattenFloatIndex(reg_idx);
|
258 regs.setFloatReg(flatIndex, val);
| 266 floatRegs.f[flatIndex] = val;
|
259 }
260
261 void setFloatRegBits(int reg_idx, FloatRegBits val)
262 {
263 int flatIndex = isa.flattenFloatIndex(reg_idx);
| 267 }
268
269 void setFloatRegBits(int reg_idx, FloatRegBits val)
270 {
271 int flatIndex = isa.flattenFloatIndex(reg_idx);
|
264 regs.setFloatRegBits(flatIndex, val);
| 272 floatRegs.i[flatIndex] = val;
|
265 }
266
267 uint64_t readPC()
268 {
269 return regs.readPC();
270 }
271
272 void setPC(uint64_t val)
273 {
274 regs.setPC(val);
275 }
276
277 uint64_t readMicroPC()
278 {
279 return microPC;
280 }
281
282 void setMicroPC(uint64_t val)
283 {
284 microPC = val;
285 }
286
287 uint64_t readNextPC()
288 {
289 return regs.readNextPC();
290 }
291
292 void setNextPC(uint64_t val)
293 {
294 regs.setNextPC(val);
295 }
296
297 uint64_t readNextMicroPC()
298 {
299 return nextMicroPC;
300 }
301
302 void setNextMicroPC(uint64_t val)
303 {
304 nextMicroPC = val;
305 }
306
307 uint64_t readNextNPC()
308 {
309 return regs.readNextNPC();
310 }
311
312 void setNextNPC(uint64_t val)
313 {
314 regs.setNextNPC(val);
315 }
316
317 MiscReg
318 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
319 {
320 return isa.readMiscRegNoEffect(misc_reg);
321 }
322
323 MiscReg
324 readMiscReg(int misc_reg, ThreadID tid = 0)
325 {
326 return isa.readMiscReg(misc_reg, tc);
327 }
328
329 void
330 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
331 {
332 return isa.setMiscRegNoEffect(misc_reg, val);
333 }
334
335 void
336 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
337 {
338 return isa.setMiscReg(misc_reg, val, tc);
339 }
340
341 int
342 flattenIntIndex(int reg)
343 {
344 return isa.flattenIntIndex(reg);
345 }
346
347 int
348 flattenFloatIndex(int reg)
349 {
350 return isa.flattenFloatIndex(reg);
351 }
352
353 unsigned readStCondFailures() { return storeCondFailures; }
354
355 void setStCondFailures(unsigned sc_failures)
356 { storeCondFailures = sc_failures; }
357
358#if !FULL_SYSTEM
359 void syscall(int64_t callnum)
360 {
361 process->syscall(callnum, tc);
362 }
363#endif
364};
365
366
367// for non-speculative execution context, spec_mode is always false
368inline bool
369SimpleThread::misspeculating()
370{
371 return false;
372}
373
374#endif // __CPU_CPU_EXEC_CONTEXT_HH__
| 273 }
274
275 uint64_t readPC()
276 {
277 return regs.readPC();
278 }
279
280 void setPC(uint64_t val)
281 {
282 regs.setPC(val);
283 }
284
285 uint64_t readMicroPC()
286 {
287 return microPC;
288 }
289
290 void setMicroPC(uint64_t val)
291 {
292 microPC = val;
293 }
294
295 uint64_t readNextPC()
296 {
297 return regs.readNextPC();
298 }
299
300 void setNextPC(uint64_t val)
301 {
302 regs.setNextPC(val);
303 }
304
305 uint64_t readNextMicroPC()
306 {
307 return nextMicroPC;
308 }
309
310 void setNextMicroPC(uint64_t val)
311 {
312 nextMicroPC = val;
313 }
314
315 uint64_t readNextNPC()
316 {
317 return regs.readNextNPC();
318 }
319
320 void setNextNPC(uint64_t val)
321 {
322 regs.setNextNPC(val);
323 }
324
325 MiscReg
326 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
327 {
328 return isa.readMiscRegNoEffect(misc_reg);
329 }
330
331 MiscReg
332 readMiscReg(int misc_reg, ThreadID tid = 0)
333 {
334 return isa.readMiscReg(misc_reg, tc);
335 }
336
337 void
338 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
339 {
340 return isa.setMiscRegNoEffect(misc_reg, val);
341 }
342
343 void
344 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
345 {
346 return isa.setMiscReg(misc_reg, val, tc);
347 }
348
349 int
350 flattenIntIndex(int reg)
351 {
352 return isa.flattenIntIndex(reg);
353 }
354
355 int
356 flattenFloatIndex(int reg)
357 {
358 return isa.flattenFloatIndex(reg);
359 }
360
361 unsigned readStCondFailures() { return storeCondFailures; }
362
363 void setStCondFailures(unsigned sc_failures)
364 { storeCondFailures = sc_failures; }
365
366#if !FULL_SYSTEM
367 void syscall(int64_t callnum)
368 {
369 process->syscall(callnum, tc);
370 }
371#endif
372};
373
374
375// for non-speculative execution context, spec_mode is always false
376inline bool
377SimpleThread::misspeculating()
378{
379 return false;
380}
381
382#endif // __CPU_CPU_EXEC_CONTEXT_HH__
|