1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa_traits.hh"
36#include "config/full_system.hh"
37#include "cpu/thread_context.hh"
38#include "cpu/thread_state.hh"
39#include "mem/physical.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/eventq.hh"
43#include "sim/host.hh"
44#include "sim/serialize.hh"
45
46class BaseCPU;
47
48#if FULL_SYSTEM
49
50#include "sim/system.hh"
51#include "arch/tlb.hh"
52
53class FunctionProfile;
54class ProfileNode;
55class FunctionalPort;
56class PhysicalPort;
57
| 1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa_traits.hh"
36#include "config/full_system.hh"
37#include "cpu/thread_context.hh"
38#include "cpu/thread_state.hh"
39#include "mem/physical.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/eventq.hh"
43#include "sim/host.hh"
44#include "sim/serialize.hh"
45
46class BaseCPU;
47
48#if FULL_SYSTEM
49
50#include "sim/system.hh"
51#include "arch/tlb.hh"
52
53class FunctionProfile;
54class ProfileNode;
55class FunctionalPort;
56class PhysicalPort;
57
|
60};
61
62#else // !FULL_SYSTEM
63
64#include "sim/process.hh"
65#include "mem/page_table.hh"
66class TranslatingPort;
67
68#endif // FULL_SYSTEM
69
70/**
71 * The SimpleThread object provides a combination of the ThreadState
72 * object and the ThreadContext interface. It implements the
73 * ThreadContext interface so that a ProxyThreadContext class can be
74 * made using SimpleThread as the template parameter (see
75 * thread_context.hh). It adds to the ThreadState object by adding all
76 * the objects needed for simple functional execution, including a
77 * simple architectural register file, and pointers to the ITB and DTB
78 * in full system mode. For CPU models that do not need more advanced
79 * ways to hold state (i.e. a separate physical register file, or
80 * separate fetch and commit PC's), this SimpleThread class provides
81 * all the necessary state for full architecture-level functional
82 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
83 * examples.
84 */
85
86class SimpleThread : public ThreadState
87{
88 protected:
89 typedef TheISA::RegFile RegFile;
90 typedef TheISA::MachInst MachInst;
91 typedef TheISA::MiscRegFile MiscRegFile;
92 typedef TheISA::MiscReg MiscReg;
93 typedef TheISA::FloatReg FloatReg;
94 typedef TheISA::FloatRegBits FloatRegBits;
95 public:
96 typedef ThreadContext::Status Status;
97
98 protected:
99 RegFile regs; // correct-path register context
100
101 public:
102 // pointer to CPU associated with this SimpleThread
103 BaseCPU *cpu;
104
105 ProxyThreadContext<SimpleThread> *tc;
106
107 System *system;
108
109#if FULL_SYSTEM
110 TheISA::ITB *itb;
111 TheISA::DTB *dtb;
112#endif
113
114 // constructor: initialize SimpleThread from given process structure
115#if FULL_SYSTEM
116 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
117 TheISA::ITB *_itb, TheISA::DTB *_dtb,
118 bool use_kernel_stats = true);
119#else
120 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
121#endif
122
123 SimpleThread();
124
125 virtual ~SimpleThread();
126
127 virtual void takeOverFrom(ThreadContext *oldContext);
128
129 void regStats(const std::string &name);
130
131 void copyTC(ThreadContext *context);
132
133 void copyState(ThreadContext *oldContext);
134
135 void serialize(std::ostream &os);
136 void unserialize(Checkpoint *cp, const std::string §ion);
137
138 /***************************************************************
139 * SimpleThread functions to provide CPU with access to various
140 * state, and to provide address translation methods.
141 **************************************************************/
142
143 /** Returns the pointer to this SimpleThread's ThreadContext. Used
144 * when a ThreadContext must be passed to objects outside of the
145 * CPU.
146 */
147 ThreadContext *getTC() { return tc; }
148
149#if FULL_SYSTEM
150 int getInstAsid() { return regs.instAsid(); }
151 int getDataAsid() { return regs.dataAsid(); }
152
153 Fault translateInstReq(RequestPtr &req)
154 {
155 return itb->translate(req, tc);
156 }
157
158 Fault translateDataReadReq(RequestPtr &req)
159 {
160 return dtb->translate(req, tc, false);
161 }
162
163 Fault translateDataWriteReq(RequestPtr &req)
164 {
165 return dtb->translate(req, tc, true);
166 }
167
168 void dumpFuncProfile();
169
170 Fault hwrei();
171
172 bool simPalCheck(int palFunc);
173#else
174
175 Fault translateInstReq(RequestPtr &req)
176 {
177 return process->pTable->translate(req);
178 }
179
180 Fault translateDataReadReq(RequestPtr &req)
181 {
182 return process->pTable->translate(req);
183 }
184
185 Fault translateDataWriteReq(RequestPtr &req)
186 {
187 return process->pTable->translate(req);
188 }
189#endif
190
191 /*******************************************
192 * ThreadContext interface functions.
193 ******************************************/
194
195 BaseCPU *getCpuPtr() { return cpu; }
196
197 int getThreadNum() { return tid; }
198
199#if FULL_SYSTEM
200 System *getSystemPtr() { return system; }
201
202 TheISA::ITB *getITBPtr() { return itb; }
203
204 TheISA::DTB *getDTBPtr() { return dtb; }
205
206 FunctionalPort *getPhysPort() { return physPort; }
207
208 /** Return a virtual port. If no thread context is specified then a static
209 * port is returned. Otherwise a port is created and returned. It must be
210 * deleted by deleteVirtPort(). */
211 VirtualPort *getVirtPort(ThreadContext *tc);
212
213 void delVirtPort(VirtualPort *vp);
214#endif
215
216 Status status() const { return _status; }
217
218 void setStatus(Status newStatus) { _status = newStatus; }
219
220 /// Set the status to Active. Optional delay indicates number of
221 /// cycles to wait before beginning execution.
222 void activate(int delay = 1);
223
224 /// Set the status to Suspended.
225 void suspend();
226
227 /// Set the status to Unallocated.
228 void deallocate();
229
230 /// Set the status to Halted.
231 void halt();
232
233/*
234 template <class T>
235 Fault read(RequestPtr &req, T &data)
236 {
237#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
238 if (req->isLocked()) {
239 req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
240 req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
241 }
242#endif
243
244 Fault error;
245 error = mem->prot_read(req->paddr, data, req->size);
246 data = LittleEndianGuest::gtoh(data);
247 return error;
248 }
249
250 template <class T>
251 Fault write(RequestPtr &req, T &data)
252 {
253#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
254 ExecContext *xc;
255
256 // If this is a store conditional, act appropriately
257 if (req->isLocked()) {
258 xc = req->xc;
259
260 if (req->isUncacheable()) {
261 // Don't update result register (see stq_c in isa_desc)
262 req->result = 2;
263 xc->setStCondFailures(0);//Needed? [RGD]
264 } else {
265 bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
266 Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
267 req->result = lock_flag;
268 if (!lock_flag ||
269 ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
270 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
271 xc->setStCondFailures(xc->readStCondFailures() + 1);
272 if (((xc->readStCondFailures()) % 100000) == 0) {
273 std::cerr << "Warning: "
274 << xc->readStCondFailures()
275 << " consecutive store conditional failures "
276 << "on cpu " << req->xc->readCpuId()
277 << std::endl;
278 }
279 return NoFault;
280 }
281 else xc->setStCondFailures(0);
282 }
283 }
284
285 // Need to clear any locked flags on other proccessors for
286 // this address. Only do this for succsful Store Conditionals
287 // and all other stores (WH64?). Unsuccessful Store
288 // Conditionals would have returned above, and wouldn't fall
289 // through.
290 for (int i = 0; i < system->execContexts.size(); i++){
291 xc = system->execContexts[i];
292 if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
293 (req->paddr & ~0xf)) {
294 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
295 }
296 }
297
298#endif
299 return mem->prot_write(req->paddr, (T)htog(data), req->size);
300 }
301*/
302 virtual bool misspeculating();
303
304 Fault instRead(RequestPtr &req)
305 {
306 panic("instRead not implemented");
307 // return funcPhysMem->read(req, inst);
308 return NoFault;
309 }
310
311 void copyArchRegs(ThreadContext *tc);
312
313 void clearArchRegs() { regs.clear(); }
314
315 //
316 // New accessors for new decoder.
317 //
318 uint64_t readIntReg(int reg_idx)
319 {
320 return regs.readIntReg(reg_idx);
321 }
322
323 FloatReg readFloatReg(int reg_idx, int width)
324 {
325 return regs.readFloatReg(reg_idx, width);
326 }
327
328 FloatReg readFloatReg(int reg_idx)
329 {
330 return regs.readFloatReg(reg_idx);
331 }
332
333 FloatRegBits readFloatRegBits(int reg_idx, int width)
334 {
335 return regs.readFloatRegBits(reg_idx, width);
336 }
337
338 FloatRegBits readFloatRegBits(int reg_idx)
339 {
340 return regs.readFloatRegBits(reg_idx);
341 }
342
343 void setIntReg(int reg_idx, uint64_t val)
344 {
345 regs.setIntReg(reg_idx, val);
346 }
347
348 void setFloatReg(int reg_idx, FloatReg val, int width)
349 {
350 regs.setFloatReg(reg_idx, val, width);
351 }
352
353 void setFloatReg(int reg_idx, FloatReg val)
354 {
355 regs.setFloatReg(reg_idx, val);
356 }
357
358 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
359 {
360 regs.setFloatRegBits(reg_idx, val, width);
361 }
362
363 void setFloatRegBits(int reg_idx, FloatRegBits val)
364 {
365 regs.setFloatRegBits(reg_idx, val);
366 }
367
368 uint64_t readPC()
369 {
370 return regs.readPC();
371 }
372
373 void setPC(uint64_t val)
374 {
375 regs.setPC(val);
376 }
377
378 uint64_t readMicroPC()
379 {
380 return microPC;
381 }
382
383 void setMicroPC(uint64_t val)
384 {
385 microPC = val;
386 }
387
388 uint64_t readNextPC()
389 {
390 return regs.readNextPC();
391 }
392
393 void setNextPC(uint64_t val)
394 {
395 regs.setNextPC(val);
396 }
397
398 uint64_t readNextMicroPC()
399 {
400 return nextMicroPC;
401 }
402
403 void setNextMicroPC(uint64_t val)
404 {
405 nextMicroPC = val;
406 }
407
408 uint64_t readNextNPC()
409 {
410 return regs.readNextNPC();
411 }
412
413 void setNextNPC(uint64_t val)
414 {
415 regs.setNextNPC(val);
416 }
417
418 MiscReg readMiscReg(int misc_reg)
419 {
420 return regs.readMiscReg(misc_reg);
421 }
422
423 MiscReg readMiscRegWithEffect(int misc_reg)
424 {
425 return regs.readMiscRegWithEffect(misc_reg, tc);
426 }
427
428 void setMiscReg(int misc_reg, const MiscReg &val)
429 {
430 return regs.setMiscReg(misc_reg, val);
431 }
432
433 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
434 {
435 return regs.setMiscRegWithEffect(misc_reg, val, tc);
436 }
437
438 unsigned readStCondFailures() { return storeCondFailures; }
439
440 void setStCondFailures(unsigned sc_failures)
441 { storeCondFailures = sc_failures; }
442
443#if !FULL_SYSTEM
444 TheISA::IntReg getSyscallArg(int i)
445 {
446 return regs.readIntReg(TheISA::ArgumentReg0 + i);
447 }
448
449 // used to shift args for indirect syscall
450 void setSyscallArg(int i, TheISA::IntReg val)
451 {
452 regs.setIntReg(TheISA::ArgumentReg0 + i, val);
453 }
454
455 void setSyscallReturn(SyscallReturn return_value)
456 {
457 TheISA::setSyscallReturn(return_value, ®s);
458 }
459
460 void syscall(int64_t callnum)
461 {
462 process->syscall(callnum, tc);
463 }
464#endif
465
466 void changeRegFileContext(TheISA::RegContextParam param,
467 TheISA::RegContextVal val)
468 {
469 regs.changeContext(param, val);
470 }
471};
472
473
474// for non-speculative execution context, spec_mode is always false
475inline bool
476SimpleThread::misspeculating()
477{
478 return false;
479}
480
481#endif // __CPU_CPU_EXEC_CONTEXT_HH__
| 62};
63
64#else // !FULL_SYSTEM
65
66#include "sim/process.hh"
67#include "mem/page_table.hh"
68class TranslatingPort;
69
70#endif // FULL_SYSTEM
71
72/**
73 * The SimpleThread object provides a combination of the ThreadState
74 * object and the ThreadContext interface. It implements the
75 * ThreadContext interface so that a ProxyThreadContext class can be
76 * made using SimpleThread as the template parameter (see
77 * thread_context.hh). It adds to the ThreadState object by adding all
78 * the objects needed for simple functional execution, including a
79 * simple architectural register file, and pointers to the ITB and DTB
80 * in full system mode. For CPU models that do not need more advanced
81 * ways to hold state (i.e. a separate physical register file, or
82 * separate fetch and commit PC's), this SimpleThread class provides
83 * all the necessary state for full architecture-level functional
84 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
85 * examples.
86 */
87
88class SimpleThread : public ThreadState
89{
90 protected:
91 typedef TheISA::RegFile RegFile;
92 typedef TheISA::MachInst MachInst;
93 typedef TheISA::MiscRegFile MiscRegFile;
94 typedef TheISA::MiscReg MiscReg;
95 typedef TheISA::FloatReg FloatReg;
96 typedef TheISA::FloatRegBits FloatRegBits;
97 public:
98 typedef ThreadContext::Status Status;
99
100 protected:
101 RegFile regs; // correct-path register context
102
103 public:
104 // pointer to CPU associated with this SimpleThread
105 BaseCPU *cpu;
106
107 ProxyThreadContext<SimpleThread> *tc;
108
109 System *system;
110
111#if FULL_SYSTEM
112 TheISA::ITB *itb;
113 TheISA::DTB *dtb;
114#endif
115
116 // constructor: initialize SimpleThread from given process structure
117#if FULL_SYSTEM
118 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
119 TheISA::ITB *_itb, TheISA::DTB *_dtb,
120 bool use_kernel_stats = true);
121#else
122 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
123#endif
124
125 SimpleThread();
126
127 virtual ~SimpleThread();
128
129 virtual void takeOverFrom(ThreadContext *oldContext);
130
131 void regStats(const std::string &name);
132
133 void copyTC(ThreadContext *context);
134
135 void copyState(ThreadContext *oldContext);
136
137 void serialize(std::ostream &os);
138 void unserialize(Checkpoint *cp, const std::string §ion);
139
140 /***************************************************************
141 * SimpleThread functions to provide CPU with access to various
142 * state, and to provide address translation methods.
143 **************************************************************/
144
145 /** Returns the pointer to this SimpleThread's ThreadContext. Used
146 * when a ThreadContext must be passed to objects outside of the
147 * CPU.
148 */
149 ThreadContext *getTC() { return tc; }
150
151#if FULL_SYSTEM
152 int getInstAsid() { return regs.instAsid(); }
153 int getDataAsid() { return regs.dataAsid(); }
154
155 Fault translateInstReq(RequestPtr &req)
156 {
157 return itb->translate(req, tc);
158 }
159
160 Fault translateDataReadReq(RequestPtr &req)
161 {
162 return dtb->translate(req, tc, false);
163 }
164
165 Fault translateDataWriteReq(RequestPtr &req)
166 {
167 return dtb->translate(req, tc, true);
168 }
169
170 void dumpFuncProfile();
171
172 Fault hwrei();
173
174 bool simPalCheck(int palFunc);
175#else
176
177 Fault translateInstReq(RequestPtr &req)
178 {
179 return process->pTable->translate(req);
180 }
181
182 Fault translateDataReadReq(RequestPtr &req)
183 {
184 return process->pTable->translate(req);
185 }
186
187 Fault translateDataWriteReq(RequestPtr &req)
188 {
189 return process->pTable->translate(req);
190 }
191#endif
192
193 /*******************************************
194 * ThreadContext interface functions.
195 ******************************************/
196
197 BaseCPU *getCpuPtr() { return cpu; }
198
199 int getThreadNum() { return tid; }
200
201#if FULL_SYSTEM
202 System *getSystemPtr() { return system; }
203
204 TheISA::ITB *getITBPtr() { return itb; }
205
206 TheISA::DTB *getDTBPtr() { return dtb; }
207
208 FunctionalPort *getPhysPort() { return physPort; }
209
210 /** Return a virtual port. If no thread context is specified then a static
211 * port is returned. Otherwise a port is created and returned. It must be
212 * deleted by deleteVirtPort(). */
213 VirtualPort *getVirtPort(ThreadContext *tc);
214
215 void delVirtPort(VirtualPort *vp);
216#endif
217
218 Status status() const { return _status; }
219
220 void setStatus(Status newStatus) { _status = newStatus; }
221
222 /// Set the status to Active. Optional delay indicates number of
223 /// cycles to wait before beginning execution.
224 void activate(int delay = 1);
225
226 /// Set the status to Suspended.
227 void suspend();
228
229 /// Set the status to Unallocated.
230 void deallocate();
231
232 /// Set the status to Halted.
233 void halt();
234
235/*
236 template <class T>
237 Fault read(RequestPtr &req, T &data)
238 {
239#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
240 if (req->isLocked()) {
241 req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
242 req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
243 }
244#endif
245
246 Fault error;
247 error = mem->prot_read(req->paddr, data, req->size);
248 data = LittleEndianGuest::gtoh(data);
249 return error;
250 }
251
252 template <class T>
253 Fault write(RequestPtr &req, T &data)
254 {
255#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
256 ExecContext *xc;
257
258 // If this is a store conditional, act appropriately
259 if (req->isLocked()) {
260 xc = req->xc;
261
262 if (req->isUncacheable()) {
263 // Don't update result register (see stq_c in isa_desc)
264 req->result = 2;
265 xc->setStCondFailures(0);//Needed? [RGD]
266 } else {
267 bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
268 Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
269 req->result = lock_flag;
270 if (!lock_flag ||
271 ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
272 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
273 xc->setStCondFailures(xc->readStCondFailures() + 1);
274 if (((xc->readStCondFailures()) % 100000) == 0) {
275 std::cerr << "Warning: "
276 << xc->readStCondFailures()
277 << " consecutive store conditional failures "
278 << "on cpu " << req->xc->readCpuId()
279 << std::endl;
280 }
281 return NoFault;
282 }
283 else xc->setStCondFailures(0);
284 }
285 }
286
287 // Need to clear any locked flags on other proccessors for
288 // this address. Only do this for succsful Store Conditionals
289 // and all other stores (WH64?). Unsuccessful Store
290 // Conditionals would have returned above, and wouldn't fall
291 // through.
292 for (int i = 0; i < system->execContexts.size(); i++){
293 xc = system->execContexts[i];
294 if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
295 (req->paddr & ~0xf)) {
296 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
297 }
298 }
299
300#endif
301 return mem->prot_write(req->paddr, (T)htog(data), req->size);
302 }
303*/
304 virtual bool misspeculating();
305
306 Fault instRead(RequestPtr &req)
307 {
308 panic("instRead not implemented");
309 // return funcPhysMem->read(req, inst);
310 return NoFault;
311 }
312
313 void copyArchRegs(ThreadContext *tc);
314
315 void clearArchRegs() { regs.clear(); }
316
317 //
318 // New accessors for new decoder.
319 //
320 uint64_t readIntReg(int reg_idx)
321 {
322 return regs.readIntReg(reg_idx);
323 }
324
325 FloatReg readFloatReg(int reg_idx, int width)
326 {
327 return regs.readFloatReg(reg_idx, width);
328 }
329
330 FloatReg readFloatReg(int reg_idx)
331 {
332 return regs.readFloatReg(reg_idx);
333 }
334
335 FloatRegBits readFloatRegBits(int reg_idx, int width)
336 {
337 return regs.readFloatRegBits(reg_idx, width);
338 }
339
340 FloatRegBits readFloatRegBits(int reg_idx)
341 {
342 return regs.readFloatRegBits(reg_idx);
343 }
344
345 void setIntReg(int reg_idx, uint64_t val)
346 {
347 regs.setIntReg(reg_idx, val);
348 }
349
350 void setFloatReg(int reg_idx, FloatReg val, int width)
351 {
352 regs.setFloatReg(reg_idx, val, width);
353 }
354
355 void setFloatReg(int reg_idx, FloatReg val)
356 {
357 regs.setFloatReg(reg_idx, val);
358 }
359
360 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
361 {
362 regs.setFloatRegBits(reg_idx, val, width);
363 }
364
365 void setFloatRegBits(int reg_idx, FloatRegBits val)
366 {
367 regs.setFloatRegBits(reg_idx, val);
368 }
369
370 uint64_t readPC()
371 {
372 return regs.readPC();
373 }
374
375 void setPC(uint64_t val)
376 {
377 regs.setPC(val);
378 }
379
380 uint64_t readMicroPC()
381 {
382 return microPC;
383 }
384
385 void setMicroPC(uint64_t val)
386 {
387 microPC = val;
388 }
389
390 uint64_t readNextPC()
391 {
392 return regs.readNextPC();
393 }
394
395 void setNextPC(uint64_t val)
396 {
397 regs.setNextPC(val);
398 }
399
400 uint64_t readNextMicroPC()
401 {
402 return nextMicroPC;
403 }
404
405 void setNextMicroPC(uint64_t val)
406 {
407 nextMicroPC = val;
408 }
409
410 uint64_t readNextNPC()
411 {
412 return regs.readNextNPC();
413 }
414
415 void setNextNPC(uint64_t val)
416 {
417 regs.setNextNPC(val);
418 }
419
420 MiscReg readMiscReg(int misc_reg)
421 {
422 return regs.readMiscReg(misc_reg);
423 }
424
425 MiscReg readMiscRegWithEffect(int misc_reg)
426 {
427 return regs.readMiscRegWithEffect(misc_reg, tc);
428 }
429
430 void setMiscReg(int misc_reg, const MiscReg &val)
431 {
432 return regs.setMiscReg(misc_reg, val);
433 }
434
435 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
436 {
437 return regs.setMiscRegWithEffect(misc_reg, val, tc);
438 }
439
440 unsigned readStCondFailures() { return storeCondFailures; }
441
442 void setStCondFailures(unsigned sc_failures)
443 { storeCondFailures = sc_failures; }
444
445#if !FULL_SYSTEM
446 TheISA::IntReg getSyscallArg(int i)
447 {
448 return regs.readIntReg(TheISA::ArgumentReg0 + i);
449 }
450
451 // used to shift args for indirect syscall
452 void setSyscallArg(int i, TheISA::IntReg val)
453 {
454 regs.setIntReg(TheISA::ArgumentReg0 + i, val);
455 }
456
457 void setSyscallReturn(SyscallReturn return_value)
458 {
459 TheISA::setSyscallReturn(return_value, ®s);
460 }
461
462 void syscall(int64_t callnum)
463 {
464 process->syscall(callnum, tc);
465 }
466#endif
467
468 void changeRegFileContext(TheISA::RegContextParam param,
469 TheISA::RegContextVal val)
470 {
471 regs.changeContext(param, val);
472 }
473};
474
475
476// for non-speculative execution context, spec_mode is always false
477inline bool
478SimpleThread::misspeculating()
479{
480 return false;
481}
482
483#endif // __CPU_CPU_EXEC_CONTEXT_HH__
|