simple_thread.hh (10934:5af8f40d8f2c) simple_thread.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2001-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 */
44
45#ifndef __CPU_SIMPLE_THREAD_HH__
46#define __CPU_SIMPLE_THREAD_HH__
47
48#include "arch/decoder.hh"
49#include "arch/isa.hh"
50#include "arch/isa_traits.hh"
51#include "arch/registers.hh"
52#include "arch/tlb.hh"
53#include "arch/types.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/thread_context.hh"
57#include "cpu/thread_state.hh"
58#include "debug/CCRegs.hh"
59#include "debug/FloatRegs.hh"
60#include "debug/IntRegs.hh"
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2001-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 */
44
45#ifndef __CPU_SIMPLE_THREAD_HH__
46#define __CPU_SIMPLE_THREAD_HH__
47
48#include "arch/decoder.hh"
49#include "arch/isa.hh"
50#include "arch/isa_traits.hh"
51#include "arch/registers.hh"
52#include "arch/tlb.hh"
53#include "arch/types.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/thread_context.hh"
57#include "cpu/thread_state.hh"
58#include "debug/CCRegs.hh"
59#include "debug/FloatRegs.hh"
60#include "debug/IntRegs.hh"
61#include "debug/VectorRegs.hh"
62#include "mem/page_table.hh"
63#include "mem/request.hh"
64#include "sim/byteswap.hh"
65#include "sim/eventq.hh"
66#include "sim/process.hh"
67#include "sim/serialize.hh"
68#include "sim/system.hh"
69
70class BaseCPU;
71class CheckerCPU;
72
73class FunctionProfile;
74class ProfileNode;
75
76namespace TheISA {
77 namespace Kernel {
78 class Statistics;
79 }
80}
81
82/**
83 * The SimpleThread object provides a combination of the ThreadState
84 * object and the ThreadContext interface. It implements the
85 * ThreadContext interface so that a ProxyThreadContext class can be
86 * made using SimpleThread as the template parameter (see
87 * thread_context.hh). It adds to the ThreadState object by adding all
88 * the objects needed for simple functional execution, including a
89 * simple architectural register file, and pointers to the ITB and DTB
90 * in full system mode. For CPU models that do not need more advanced
91 * ways to hold state (i.e. a separate physical register file, or
92 * separate fetch and commit PC's), this SimpleThread class provides
93 * all the necessary state for full architecture-level functional
94 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
95 * examples.
96 */
97
98class SimpleThread : public ThreadState
99{
100 protected:
101 typedef TheISA::MachInst MachInst;
102 typedef TheISA::MiscReg MiscReg;
103 typedef TheISA::FloatReg FloatReg;
104 typedef TheISA::FloatRegBits FloatRegBits;
105 typedef TheISA::CCReg CCReg;
61#include "mem/page_table.hh"
62#include "mem/request.hh"
63#include "sim/byteswap.hh"
64#include "sim/eventq.hh"
65#include "sim/process.hh"
66#include "sim/serialize.hh"
67#include "sim/system.hh"
68
69class BaseCPU;
70class CheckerCPU;
71
72class FunctionProfile;
73class ProfileNode;
74
75namespace TheISA {
76 namespace Kernel {
77 class Statistics;
78 }
79}
80
81/**
82 * The SimpleThread object provides a combination of the ThreadState
83 * object and the ThreadContext interface. It implements the
84 * ThreadContext interface so that a ProxyThreadContext class can be
85 * made using SimpleThread as the template parameter (see
86 * thread_context.hh). It adds to the ThreadState object by adding all
87 * the objects needed for simple functional execution, including a
88 * simple architectural register file, and pointers to the ITB and DTB
89 * in full system mode. For CPU models that do not need more advanced
90 * ways to hold state (i.e. a separate physical register file, or
91 * separate fetch and commit PC's), this SimpleThread class provides
92 * all the necessary state for full architecture-level functional
93 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
94 * examples.
95 */
96
97class SimpleThread : public ThreadState
98{
99 protected:
100 typedef TheISA::MachInst MachInst;
101 typedef TheISA::MiscReg MiscReg;
102 typedef TheISA::FloatReg FloatReg;
103 typedef TheISA::FloatRegBits FloatRegBits;
104 typedef TheISA::CCReg CCReg;
106 typedef TheISA::VectorReg VectorReg;
107
108 public:
109 typedef ThreadContext::Status Status;
110
111 protected:
112 union {
113 FloatReg f[TheISA::NumFloatRegs];
114 FloatRegBits i[TheISA::NumFloatRegs];
115 } floatRegs;
116 TheISA::IntReg intRegs[TheISA::NumIntRegs];
105 public:
106 typedef ThreadContext::Status Status;
107
108 protected:
109 union {
110 FloatReg f[TheISA::NumFloatRegs];
111 FloatRegBits i[TheISA::NumFloatRegs];
112 } floatRegs;
113 TheISA::IntReg intRegs[TheISA::NumIntRegs];
117
118#ifdef ISA_HAS_CC_REGS
119 TheISA::CCReg ccRegs[TheISA::NumCCRegs];
120#endif
114#ifdef ISA_HAS_CC_REGS
115 TheISA::CCReg ccRegs[TheISA::NumCCRegs];
116#endif
121
122#ifdef ISA_HAS_VECTOR_REGS
123 TheISA::VectorReg vectorRegs[TheISA::NumVectorRegs];
124#endif
125
126 TheISA::ISA *const isa; // one "instance" of the current ISA.
127
128 TheISA::PCState _pcState;
129
130 /** Did this instruction execute or is it predicated false */
131 bool predicate;
132
133 public:
134 std::string name() const
135 {
136 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
137 }
138
139 ProxyThreadContext<SimpleThread> *tc;
140
141 System *system;
142
143 TheISA::TLB *itb;
144 TheISA::TLB *dtb;
145
146 TheISA::Decoder decoder;
147
148 // constructor: initialize SimpleThread from given process structure
149 // FS
150 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
151 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
152 bool use_kernel_stats = true);
153 // SE
154 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
155 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
156 TheISA::ISA *_isa);
157
158 virtual ~SimpleThread();
159
160 virtual void takeOverFrom(ThreadContext *oldContext);
161
162 void regStats(const std::string &name);
163
164 void copyState(ThreadContext *oldContext);
165
166 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
167 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
168 void startup();
169
170 /***************************************************************
171 * SimpleThread functions to provide CPU with access to various
172 * state.
173 **************************************************************/
174
175 /** Returns the pointer to this SimpleThread's ThreadContext. Used
176 * when a ThreadContext must be passed to objects outside of the
177 * CPU.
178 */
179 ThreadContext *getTC() { return tc; }
180
181 void demapPage(Addr vaddr, uint64_t asn)
182 {
183 itb->demapPage(vaddr, asn);
184 dtb->demapPage(vaddr, asn);
185 }
186
187 void demapInstPage(Addr vaddr, uint64_t asn)
188 {
189 itb->demapPage(vaddr, asn);
190 }
191
192 void demapDataPage(Addr vaddr, uint64_t asn)
193 {
194 dtb->demapPage(vaddr, asn);
195 }
196
197 void dumpFuncProfile();
198
199 Fault hwrei();
200
201 bool simPalCheck(int palFunc);
202
203 /*******************************************
204 * ThreadContext interface functions.
205 ******************************************/
206
207 BaseCPU *getCpuPtr() { return baseCpu; }
208
209 TheISA::TLB *getITBPtr() { return itb; }
210
211 TheISA::TLB *getDTBPtr() { return dtb; }
212
213 CheckerCPU *getCheckerCpuPtr() { return NULL; }
214
215 TheISA::Decoder *getDecoderPtr() { return &decoder; }
216
217 System *getSystemPtr() { return system; }
218
219 Status status() const { return _status; }
220
221 void setStatus(Status newStatus) { _status = newStatus; }
222
223 /// Set the status to Active.
224 void activate();
225
226 /// Set the status to Suspended.
227 void suspend();
228
229 /// Set the status to Halted.
230 void halt();
231
232 void copyArchRegs(ThreadContext *tc);
233
234 void clearArchRegs()
235 {
236 _pcState = 0;
237 memset(intRegs, 0, sizeof(intRegs));
238 memset(floatRegs.i, 0, sizeof(floatRegs.i));
239#ifdef ISA_HAS_CC_REGS
240 memset(ccRegs, 0, sizeof(ccRegs));
241#endif
242 isa->clear();
243 }
244
245 //
246 // New accessors for new decoder.
247 //
248 uint64_t readIntReg(int reg_idx)
249 {
250 int flatIndex = isa->flattenIntIndex(reg_idx);
251 assert(flatIndex < TheISA::NumIntRegs);
252 uint64_t regVal(readIntRegFlat(flatIndex));
253 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
254 reg_idx, flatIndex, regVal);
255 return regVal;
256 }
257
258 FloatReg readFloatReg(int reg_idx)
259 {
260 int flatIndex = isa->flattenFloatIndex(reg_idx);
261 assert(flatIndex < TheISA::NumFloatRegs);
262 FloatReg regVal(readFloatRegFlat(flatIndex));
263 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
264 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
265 return regVal;
266 }
267
268 FloatRegBits readFloatRegBits(int reg_idx)
269 {
270 int flatIndex = isa->flattenFloatIndex(reg_idx);
271 assert(flatIndex < TheISA::NumFloatRegs);
272 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
273 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
274 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
275 return regVal;
276 }
277
278 CCReg readCCReg(int reg_idx)
279 {
280#ifdef ISA_HAS_CC_REGS
281 int flatIndex = isa->flattenCCIndex(reg_idx);
282 assert(0 <= flatIndex);
283 assert(flatIndex < TheISA::NumCCRegs);
284 uint64_t regVal(readCCRegFlat(flatIndex));
285 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
286 reg_idx, flatIndex, regVal);
287 return regVal;
288#else
289 panic("Tried to read a CC register.");
290 return 0;
291#endif
292 }
293
117 TheISA::ISA *const isa; // one "instance" of the current ISA.
118
119 TheISA::PCState _pcState;
120
121 /** Did this instruction execute or is it predicated false */
122 bool predicate;
123
124 public:
125 std::string name() const
126 {
127 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
128 }
129
130 ProxyThreadContext<SimpleThread> *tc;
131
132 System *system;
133
134 TheISA::TLB *itb;
135 TheISA::TLB *dtb;
136
137 TheISA::Decoder decoder;
138
139 // constructor: initialize SimpleThread from given process structure
140 // FS
141 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
142 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
143 bool use_kernel_stats = true);
144 // SE
145 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
146 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
147 TheISA::ISA *_isa);
148
149 virtual ~SimpleThread();
150
151 virtual void takeOverFrom(ThreadContext *oldContext);
152
153 void regStats(const std::string &name);
154
155 void copyState(ThreadContext *oldContext);
156
157 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
158 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
159 void startup();
160
161 /***************************************************************
162 * SimpleThread functions to provide CPU with access to various
163 * state.
164 **************************************************************/
165
166 /** Returns the pointer to this SimpleThread's ThreadContext. Used
167 * when a ThreadContext must be passed to objects outside of the
168 * CPU.
169 */
170 ThreadContext *getTC() { return tc; }
171
172 void demapPage(Addr vaddr, uint64_t asn)
173 {
174 itb->demapPage(vaddr, asn);
175 dtb->demapPage(vaddr, asn);
176 }
177
178 void demapInstPage(Addr vaddr, uint64_t asn)
179 {
180 itb->demapPage(vaddr, asn);
181 }
182
183 void demapDataPage(Addr vaddr, uint64_t asn)
184 {
185 dtb->demapPage(vaddr, asn);
186 }
187
188 void dumpFuncProfile();
189
190 Fault hwrei();
191
192 bool simPalCheck(int palFunc);
193
194 /*******************************************
195 * ThreadContext interface functions.
196 ******************************************/
197
198 BaseCPU *getCpuPtr() { return baseCpu; }
199
200 TheISA::TLB *getITBPtr() { return itb; }
201
202 TheISA::TLB *getDTBPtr() { return dtb; }
203
204 CheckerCPU *getCheckerCpuPtr() { return NULL; }
205
206 TheISA::Decoder *getDecoderPtr() { return &decoder; }
207
208 System *getSystemPtr() { return system; }
209
210 Status status() const { return _status; }
211
212 void setStatus(Status newStatus) { _status = newStatus; }
213
214 /// Set the status to Active.
215 void activate();
216
217 /// Set the status to Suspended.
218 void suspend();
219
220 /// Set the status to Halted.
221 void halt();
222
223 void copyArchRegs(ThreadContext *tc);
224
225 void clearArchRegs()
226 {
227 _pcState = 0;
228 memset(intRegs, 0, sizeof(intRegs));
229 memset(floatRegs.i, 0, sizeof(floatRegs.i));
230#ifdef ISA_HAS_CC_REGS
231 memset(ccRegs, 0, sizeof(ccRegs));
232#endif
233 isa->clear();
234 }
235
236 //
237 // New accessors for new decoder.
238 //
239 uint64_t readIntReg(int reg_idx)
240 {
241 int flatIndex = isa->flattenIntIndex(reg_idx);
242 assert(flatIndex < TheISA::NumIntRegs);
243 uint64_t regVal(readIntRegFlat(flatIndex));
244 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
245 reg_idx, flatIndex, regVal);
246 return regVal;
247 }
248
249 FloatReg readFloatReg(int reg_idx)
250 {
251 int flatIndex = isa->flattenFloatIndex(reg_idx);
252 assert(flatIndex < TheISA::NumFloatRegs);
253 FloatReg regVal(readFloatRegFlat(flatIndex));
254 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
255 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
256 return regVal;
257 }
258
259 FloatRegBits readFloatRegBits(int reg_idx)
260 {
261 int flatIndex = isa->flattenFloatIndex(reg_idx);
262 assert(flatIndex < TheISA::NumFloatRegs);
263 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
264 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
265 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
266 return regVal;
267 }
268
269 CCReg readCCReg(int reg_idx)
270 {
271#ifdef ISA_HAS_CC_REGS
272 int flatIndex = isa->flattenCCIndex(reg_idx);
273 assert(0 <= flatIndex);
274 assert(flatIndex < TheISA::NumCCRegs);
275 uint64_t regVal(readCCRegFlat(flatIndex));
276 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
277 reg_idx, flatIndex, regVal);
278 return regVal;
279#else
280 panic("Tried to read a CC register.");
281 return 0;
282#endif
283 }
284
294 const VectorReg &readVectorReg(int reg_idx)
295 {
296 int flatIndex = isa->flattenVectorIndex(reg_idx);
297 assert(0 <= flatIndex);
298 assert(flatIndex < TheISA::NumVectorRegs);
299 DPRINTF(VectorRegs, "Reading vector reg %d (%d).\n",
300 reg_idx, flatIndex);
301 return readVectorRegFlat(flatIndex);
302 }
303
304 void setIntReg(int reg_idx, uint64_t val)
305 {
306 int flatIndex = isa->flattenIntIndex(reg_idx);
307 assert(flatIndex < TheISA::NumIntRegs);
308 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
309 reg_idx, flatIndex, val);
310 setIntRegFlat(flatIndex, val);
311 }
312
313 void setFloatReg(int reg_idx, FloatReg val)
314 {
315 int flatIndex = isa->flattenFloatIndex(reg_idx);
316 assert(flatIndex < TheISA::NumFloatRegs);
317 setFloatRegFlat(flatIndex, val);
318 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
319 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
320 }
321
322 void setFloatRegBits(int reg_idx, FloatRegBits val)
323 {
324 int flatIndex = isa->flattenFloatIndex(reg_idx);
325 assert(flatIndex < TheISA::NumFloatRegs);
326 // XXX: Fix array out of bounds compiler error for gem5.fast
327 // when checkercpu enabled
328 if (flatIndex < TheISA::NumFloatRegs)
329 setFloatRegBitsFlat(flatIndex, val);
330 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
331 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
332 }
333
334 void setCCReg(int reg_idx, CCReg val)
335 {
336#ifdef ISA_HAS_CC_REGS
337 int flatIndex = isa->flattenCCIndex(reg_idx);
338 assert(flatIndex < TheISA::NumCCRegs);
339 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
340 reg_idx, flatIndex, val);
341 setCCRegFlat(flatIndex, val);
342#else
343 panic("Tried to set a CC register.");
344#endif
345 }
346
285 void setIntReg(int reg_idx, uint64_t val)
286 {
287 int flatIndex = isa->flattenIntIndex(reg_idx);
288 assert(flatIndex < TheISA::NumIntRegs);
289 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
290 reg_idx, flatIndex, val);
291 setIntRegFlat(flatIndex, val);
292 }
293
294 void setFloatReg(int reg_idx, FloatReg val)
295 {
296 int flatIndex = isa->flattenFloatIndex(reg_idx);
297 assert(flatIndex < TheISA::NumFloatRegs);
298 setFloatRegFlat(flatIndex, val);
299 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
300 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
301 }
302
303 void setFloatRegBits(int reg_idx, FloatRegBits val)
304 {
305 int flatIndex = isa->flattenFloatIndex(reg_idx);
306 assert(flatIndex < TheISA::NumFloatRegs);
307 // XXX: Fix array out of bounds compiler error for gem5.fast
308 // when checkercpu enabled
309 if (flatIndex < TheISA::NumFloatRegs)
310 setFloatRegBitsFlat(flatIndex, val);
311 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
312 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
313 }
314
315 void setCCReg(int reg_idx, CCReg val)
316 {
317#ifdef ISA_HAS_CC_REGS
318 int flatIndex = isa->flattenCCIndex(reg_idx);
319 assert(flatIndex < TheISA::NumCCRegs);
320 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
321 reg_idx, flatIndex, val);
322 setCCRegFlat(flatIndex, val);
323#else
324 panic("Tried to set a CC register.");
325#endif
326 }
327
347 void setVectorReg(int reg_idx, const VectorReg &val)
348 {
349#ifdef ISA_HAS_VECTOR_REGS
350 int flatIndex = isa->flattenVectorIndex(reg_idx);
351 assert(flatIndex < TheISA::NumVectorRegs);
352 DPRINTF(VectorRegs, "Setting vector reg %d (%d).\n",
353 reg_idx, flatIndex);
354 setVectorRegFlat(flatIndex, val);
355#else
356 panic("Tried to set a vector register.");
357#endif
358 }
359
360 TheISA::PCState
361 pcState()
362 {
363 return _pcState;
364 }
365
366 void
367 pcState(const TheISA::PCState &val)
368 {
369 _pcState = val;
370 }
371
372 void
373 pcStateNoRecord(const TheISA::PCState &val)
374 {
375 _pcState = val;
376 }
377
378 Addr
379 instAddr()
380 {
381 return _pcState.instAddr();
382 }
383
384 Addr
385 nextInstAddr()
386 {
387 return _pcState.nextInstAddr();
388 }
389
390 MicroPC
391 microPC()
392 {
393 return _pcState.microPC();
394 }
395
396 bool readPredicate()
397 {
398 return predicate;
399 }
400
401 void setPredicate(bool val)
402 {
403 predicate = val;
404 }
405
406 MiscReg
407 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
408 {
409 return isa->readMiscRegNoEffect(misc_reg);
410 }
411
412 MiscReg
413 readMiscReg(int misc_reg, ThreadID tid = 0)
414 {
415 return isa->readMiscReg(misc_reg, tc);
416 }
417
418 void
419 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
420 {
421 return isa->setMiscRegNoEffect(misc_reg, val);
422 }
423
424 void
425 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
426 {
427 return isa->setMiscReg(misc_reg, val, tc);
428 }
429
430 int
431 flattenIntIndex(int reg)
432 {
433 return isa->flattenIntIndex(reg);
434 }
435
436 int
437 flattenFloatIndex(int reg)
438 {
439 return isa->flattenFloatIndex(reg);
440 }
441
442 int
443 flattenCCIndex(int reg)
444 {
445 return isa->flattenCCIndex(reg);
446 }
447
448 int
328 TheISA::PCState
329 pcState()
330 {
331 return _pcState;
332 }
333
334 void
335 pcState(const TheISA::PCState &val)
336 {
337 _pcState = val;
338 }
339
340 void
341 pcStateNoRecord(const TheISA::PCState &val)
342 {
343 _pcState = val;
344 }
345
346 Addr
347 instAddr()
348 {
349 return _pcState.instAddr();
350 }
351
352 Addr
353 nextInstAddr()
354 {
355 return _pcState.nextInstAddr();
356 }
357
358 MicroPC
359 microPC()
360 {
361 return _pcState.microPC();
362 }
363
364 bool readPredicate()
365 {
366 return predicate;
367 }
368
369 void setPredicate(bool val)
370 {
371 predicate = val;
372 }
373
374 MiscReg
375 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
376 {
377 return isa->readMiscRegNoEffect(misc_reg);
378 }
379
380 MiscReg
381 readMiscReg(int misc_reg, ThreadID tid = 0)
382 {
383 return isa->readMiscReg(misc_reg, tc);
384 }
385
386 void
387 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
388 {
389 return isa->setMiscRegNoEffect(misc_reg, val);
390 }
391
392 void
393 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
394 {
395 return isa->setMiscReg(misc_reg, val, tc);
396 }
397
398 int
399 flattenIntIndex(int reg)
400 {
401 return isa->flattenIntIndex(reg);
402 }
403
404 int
405 flattenFloatIndex(int reg)
406 {
407 return isa->flattenFloatIndex(reg);
408 }
409
410 int
411 flattenCCIndex(int reg)
412 {
413 return isa->flattenCCIndex(reg);
414 }
415
416 int
449 flattenVectorIndex(int reg)
450 {
451 return isa->flattenVectorIndex(reg);
452 }
453
454 int
455 flattenMiscIndex(int reg)
456 {
457 return isa->flattenMiscIndex(reg);
458 }
459
460 unsigned readStCondFailures() { return storeCondFailures; }
461
462 void setStCondFailures(unsigned sc_failures)
463 { storeCondFailures = sc_failures; }
464
465 void syscall(int64_t callnum)
466 {
467 process->syscall(callnum, tc);
468 }
469
470 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
471 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
472
473 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
474 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
475
476 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
477 void setFloatRegBitsFlat(int idx, FloatRegBits val) {
478 floatRegs.i[idx] = val;
479 }
480
481#ifdef ISA_HAS_CC_REGS
482 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
483 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
484#else
485 CCReg readCCRegFlat(int idx)
486 { panic("readCCRegFlat w/no CC regs!\n"); }
487
488 void setCCRegFlat(int idx, CCReg val)
489 { panic("setCCRegFlat w/no CC regs!\n"); }
490#endif
417 flattenMiscIndex(int reg)
418 {
419 return isa->flattenMiscIndex(reg);
420 }
421
422 unsigned readStCondFailures() { return storeCondFailures; }
423
424 void setStCondFailures(unsigned sc_failures)
425 { storeCondFailures = sc_failures; }
426
427 void syscall(int64_t callnum)
428 {
429 process->syscall(callnum, tc);
430 }
431
432 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
433 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
434
435 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
436 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
437
438 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
439 void setFloatRegBitsFlat(int idx, FloatRegBits val) {
440 floatRegs.i[idx] = val;
441 }
442
443#ifdef ISA_HAS_CC_REGS
444 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
445 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
446#else
447 CCReg readCCRegFlat(int idx)
448 { panic("readCCRegFlat w/no CC regs!\n"); }
449
450 void setCCRegFlat(int idx, CCReg val)
451 { panic("setCCRegFlat w/no CC regs!\n"); }
452#endif
491
492#ifdef ISA_HAS_VECTOR_REGS
493 const VectorReg &readVectorRegFlat(int idx) { return vectorRegs[idx]; }
494 void setVectorRegFlat(int idx, const VectorReg &val)
495 { vectorRegs[idx] = val; }
496#else
497 const VectorReg &readVectorRegFlat(int idx)
498 { panic("readVectorRegFlat w/no Vector regs!\n"); }
499
500 void setVectorRegFlat(int idx, const VectorReg &val)
501 { panic("setVectorRegFlat w/no Vector regs!\n"); }
502#endif
503};
504
505
506#endif // __CPU_CPU_EXEC_CONTEXT_HH__
453};
454
455
456#endif // __CPU_CPU_EXEC_CONTEXT_HH__