1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Nathan Binkert
42 */
43
44#ifndef __CPU_SIMPLE_THREAD_HH__
45#define __CPU_SIMPLE_THREAD_HH__
46
47#include "arch/decoder.hh"
48#include "arch/isa.hh"
49#include "arch/isa_traits.hh"
50#include "arch/registers.hh"
51#include "arch/tlb.hh"
52#include "arch/types.hh"
53#include "base/types.hh"
54#include "config/the_isa.hh"
55#include "cpu/thread_context.hh"
56#include "cpu/thread_state.hh"
57#include "debug/FloatRegs.hh"
58#include "debug/IntRegs.hh"
59#include "mem/page_table.hh"
60#include "mem/request.hh"
61#include "sim/byteswap.hh"
62#include "sim/eventq.hh"
63#include "sim/process.hh"
64#include "sim/serialize.hh"
65#include "sim/system.hh"
66
67class BaseCPU;
68class CheckerCPU;
69
70class FunctionProfile;
71class ProfileNode;
72
73namespace TheISA {
74 namespace Kernel {
75 class Statistics;
76 }
77}
78
79/**
80 * The SimpleThread object provides a combination of the ThreadState
81 * object and the ThreadContext interface. It implements the
82 * ThreadContext interface so that a ProxyThreadContext class can be
83 * made using SimpleThread as the template parameter (see
84 * thread_context.hh). It adds to the ThreadState object by adding all
85 * the objects needed for simple functional execution, including a
86 * simple architectural register file, and pointers to the ITB and DTB
87 * in full system mode. For CPU models that do not need more advanced
88 * ways to hold state (i.e. a separate physical register file, or
89 * separate fetch and commit PC's), this SimpleThread class provides
90 * all the necessary state for full architecture-level functional
91 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
92 * examples.
93 */
94
95class SimpleThread : public ThreadState
96{
97 protected:
98 typedef TheISA::MachInst MachInst;
99 typedef TheISA::MiscReg MiscReg;
100 typedef TheISA::FloatReg FloatReg;
101 typedef TheISA::FloatRegBits FloatRegBits;
102 public:
103 typedef ThreadContext::Status Status;
104
105 protected:
106 union {
107 FloatReg f[TheISA::NumFloatRegs];
108 FloatRegBits i[TheISA::NumFloatRegs];
109 } floatRegs;
110 TheISA::IntReg intRegs[TheISA::NumIntRegs];
111 TheISA::ISA *const isa; // one "instance" of the current ISA.
112
113 TheISA::PCState _pcState;
114
115 /** Did this instruction execute or is it predicated false */
116 bool predicate;
117
118 public:
119 std::string name() const
120 {
121 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
122 }
123
124 ProxyThreadContext<SimpleThread> *tc;
125
126 System *system;
127
128 TheISA::TLB *itb;
129 TheISA::TLB *dtb;
130
131 TheISA::Decoder decoder;
132
133 // constructor: initialize SimpleThread from given process structure
134 // FS
135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
136 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
137 bool use_kernel_stats = true);
138 // SE
139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
140 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
141 TheISA::ISA *_isa);
142
143 virtual ~SimpleThread();
144
145 virtual void takeOverFrom(ThreadContext *oldContext);
146
147 void regStats(const std::string &name);
148
149 void copyState(ThreadContext *oldContext);
150
151 void serialize(std::ostream &os);
152 void unserialize(Checkpoint *cp, const std::string &section);
153
154 /***************************************************************
155 * SimpleThread functions to provide CPU with access to various
156 * state.
157 **************************************************************/
158
159 /** Returns the pointer to this SimpleThread's ThreadContext. Used
160 * when a ThreadContext must be passed to objects outside of the
161 * CPU.
162 */
163 ThreadContext *getTC() { return tc; }
164
165 void demapPage(Addr vaddr, uint64_t asn)
166 {
167 itb->demapPage(vaddr, asn);
168 dtb->demapPage(vaddr, asn);
169 }
170
171 void demapInstPage(Addr vaddr, uint64_t asn)
172 {
173 itb->demapPage(vaddr, asn);
174 }
175
176 void demapDataPage(Addr vaddr, uint64_t asn)
177 {
178 dtb->demapPage(vaddr, asn);
179 }
180
181 void dumpFuncProfile();
182
183 Fault hwrei();
184
185 bool simPalCheck(int palFunc);
186
187 /*******************************************
188 * ThreadContext interface functions.
189 ******************************************/
190
191 BaseCPU *getCpuPtr() { return baseCpu; }
192
193 TheISA::TLB *getITBPtr() { return itb; }
194
195 TheISA::TLB *getDTBPtr() { return dtb; }
196
197 CheckerCPU *getCheckerCpuPtr() { return NULL; }
198
199 TheISA::Decoder *getDecoderPtr() { return &decoder; }
200
201 System *getSystemPtr() { return system; }
202
203 Status status() const { return _status; }
204
205 void setStatus(Status newStatus) { _status = newStatus; }
206
207 /// Set the status to Active. Optional delay indicates number of
208 /// cycles to wait before beginning execution.
209 void activate(Cycles delay = Cycles(1));
210
211 /// Set the status to Suspended.
212 void suspend();
213
214 /// Set the status to Halted.
215 void halt();
216
217 virtual bool misspeculating();
218
219 void copyArchRegs(ThreadContext *tc);
220
221 void clearArchRegs()
222 {
223 _pcState = 0;
224 memset(intRegs, 0, sizeof(intRegs));
225 memset(floatRegs.i, 0, sizeof(floatRegs.i));
226 isa->clear();
227 }
228
229 //
230 // New accessors for new decoder.
231 //
232 uint64_t readIntReg(int reg_idx)
233 {
234 int flatIndex = isa->flattenIntIndex(reg_idx);
235 assert(flatIndex < TheISA::NumIntRegs);
236 uint64_t regVal(readIntRegFlat(flatIndex));
237 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
238 reg_idx, flatIndex, regVal);
239 return regVal;
240 }
241
242 FloatReg readFloatReg(int reg_idx)
243 {
244 int flatIndex = isa->flattenFloatIndex(reg_idx);
245 assert(flatIndex < TheISA::NumFloatRegs);
246 FloatReg regVal(readFloatRegFlat(flatIndex));
247 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
248 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
249 return regVal;
250 }
251
252 FloatRegBits readFloatRegBits(int reg_idx)
253 {
254 int flatIndex = isa->flattenFloatIndex(reg_idx);
255 assert(flatIndex < TheISA::NumFloatRegs);
256 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
257 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
258 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
259 return regVal;
260 }
261
262 void setIntReg(int reg_idx, uint64_t val)
263 {
264 int flatIndex = isa->flattenIntIndex(reg_idx);
265 assert(flatIndex < TheISA::NumIntRegs);
266 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
267 reg_idx, flatIndex, val);
268 setIntRegFlat(flatIndex, val);
269 }
270
271 void setFloatReg(int reg_idx, FloatReg val)
272 {
273 int flatIndex = isa->flattenFloatIndex(reg_idx);
274 assert(flatIndex < TheISA::NumFloatRegs);
275 setFloatRegFlat(flatIndex, val);
276 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
277 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
278 }
279
280 void setFloatRegBits(int reg_idx, FloatRegBits val)
281 {
282 int flatIndex = isa->flattenFloatIndex(reg_idx);
283 assert(flatIndex < TheISA::NumFloatRegs);
284 // XXX: Fix array out of bounds compiler error for gem5.fast
285 // when checkercpu enabled
286 if (flatIndex < TheISA::NumFloatRegs)
287 setFloatRegBitsFlat(flatIndex, val);
288 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
289 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
290 }
291
292 TheISA::PCState
293 pcState()
294 {
295 return _pcState;
296 }
297
298 void
299 pcState(const TheISA::PCState &val)
300 {
301 _pcState = val;
302 }
303
304 void
305 pcStateNoRecord(const TheISA::PCState &val)
306 {
307 _pcState = val;
308 }
309
310 Addr
311 instAddr()
312 {
313 return _pcState.instAddr();
314 }
315
316 Addr
317 nextInstAddr()
318 {
319 return _pcState.nextInstAddr();
320 }
321
322 MicroPC
323 microPC()
324 {
325 return _pcState.microPC();
326 }
327
328 bool readPredicate()
329 {
330 return predicate;
331 }
332
333 void setPredicate(bool val)
334 {
335 predicate = val;
336 }
337
338 MiscReg
339 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
340 {
341 return isa->readMiscRegNoEffect(misc_reg);
342 }
343
344 MiscReg
345 readMiscReg(int misc_reg, ThreadID tid = 0)
346 {
347 return isa->readMiscReg(misc_reg, tc);
348 }
349
350 void
351 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
352 {
353 return isa->setMiscRegNoEffect(misc_reg, val);
354 }
355
356 void
357 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
358 {
359 return isa->setMiscReg(misc_reg, val, tc);
360 }
361
362 int
363 flattenIntIndex(int reg)
364 {
365 return isa->flattenIntIndex(reg);
366 }
367
368 int
369 flattenFloatIndex(int reg)
370 {
371 return isa->flattenFloatIndex(reg);
372 }
373
374 unsigned readStCondFailures() { return storeCondFailures; }
375
376 void setStCondFailures(unsigned sc_failures)
377 { storeCondFailures = sc_failures; }
378
379 void syscall(int64_t callnum)
380 {
381 process->syscall(callnum, tc);
382 }
383
384 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
385 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
386
387 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
388 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
389
390 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
391 void setFloatRegBitsFlat(int idx, FloatRegBits val) {
392 floatRegs.i[idx] = val;
393 }
394
395};
396
397
398// for non-speculative execution context, spec_mode is always false
399inline bool
400SimpleThread::misspeculating()
401{
402 return false;
403}
404
405#endif // __CPU_CPU_EXEC_CONTEXT_HH__