1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa_traits.hh"
36#include "arch/regfile.hh"
37#include "arch/syscallreturn.hh"
38#include "arch/tlb.hh"
39#include "config/full_system.hh"
40#include "cpu/thread_context.hh"
41#include "cpu/thread_state.hh"
42#include "mem/request.hh"
43#include "sim/byteswap.hh"
44#include "sim/eventq.hh"
45#include "sim/host.hh"
46#include "sim/serialize.hh"
47
48class BaseCPU;
49
50#if FULL_SYSTEM
51
52#include "sim/system.hh"
53
54class FunctionProfile;
55class ProfileNode;
56class FunctionalPort;
57class PhysicalPort;
58
59namespace TheISA {
60 namespace Kernel {
61 class Statistics;
62 };
63};
64
65#else // !FULL_SYSTEM
66
67#include "sim/process.hh"
68#include "mem/page_table.hh"
69class TranslatingPort;
70
71#endif // FULL_SYSTEM
72
73/**
74 * The SimpleThread object provides a combination of the ThreadState
75 * object and the ThreadContext interface. It implements the
76 * ThreadContext interface so that a ProxyThreadContext class can be
77 * made using SimpleThread as the template parameter (see
78 * thread_context.hh). It adds to the ThreadState object by adding all
79 * the objects needed for simple functional execution, including a
80 * simple architectural register file, and pointers to the ITB and DTB
81 * in full system mode. For CPU models that do not need more advanced
82 * ways to hold state (i.e. a separate physical register file, or
83 * separate fetch and commit PC's), this SimpleThread class provides
84 * all the necessary state for full architecture-level functional
85 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
86 * examples.
87 */
88
89class SimpleThread : public ThreadState
90{
91 protected:
92 typedef TheISA::RegFile RegFile;
93 typedef TheISA::MachInst MachInst;
94 typedef TheISA::MiscRegFile MiscRegFile;
95 typedef TheISA::MiscReg MiscReg;
96 typedef TheISA::FloatReg FloatReg;
97 typedef TheISA::FloatRegBits FloatRegBits;
98 public:
99 typedef ThreadContext::Status Status;
100
101 protected:
102 RegFile regs; // correct-path register context
103
104 public:
105 // pointer to CPU associated with this SimpleThread
106 BaseCPU *cpu;
107
108 ProxyThreadContext<SimpleThread> *tc;
109
110 System *system;
111
112 TheISA::ITB *itb;
113 TheISA::DTB *dtb;
114
115 // constructor: initialize SimpleThread from given process structure
116#if FULL_SYSTEM
117 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
118 TheISA::ITB *_itb, TheISA::DTB *_dtb,
119 bool use_kernel_stats = true);
120#else
121 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
122 TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
123#endif
124
125 SimpleThread();
126
127 virtual ~SimpleThread();
128
129 virtual void takeOverFrom(ThreadContext *oldContext);
130
131 void regStats(const std::string &name);
132
133 void copyTC(ThreadContext *context);
134
135 void copyState(ThreadContext *oldContext);
136
137 void serialize(std::ostream &os);
138 void unserialize(Checkpoint *cp, const std::string &section);
139
140 /***************************************************************
141 * SimpleThread functions to provide CPU with access to various
142 * state, and to provide address translation methods.
143 **************************************************************/
144
145 /** Returns the pointer to this SimpleThread's ThreadContext. Used
146 * when a ThreadContext must be passed to objects outside of the
147 * CPU.
148 */
149 ThreadContext *getTC() { return tc; }
150
151 Fault translateInstReq(RequestPtr &req)
152 {
153 return itb->translate(req, tc);
154 }
155
156 Fault translateDataReadReq(RequestPtr &req)
157 {
158 return dtb->translate(req, tc, false);
159 }
160
161 Fault translateDataWriteReq(RequestPtr &req)
162 {
163 return dtb->translate(req, tc, true);
164 }
165
166 void demapPage(Addr vaddr, uint64_t asn)
167 {
168 itb->demapPage(vaddr, asn);
169 dtb->demapPage(vaddr, asn);
170 }
171
172 void demapInstPage(Addr vaddr, uint64_t asn)
173 {
174 itb->demapPage(vaddr, asn);
175 }
176
177 void demapDataPage(Addr vaddr, uint64_t asn)
178 {
179 dtb->demapPage(vaddr, asn);
180 }
181
182#if FULL_SYSTEM
183 int getInstAsid() { return regs.instAsid(); }
184 int getDataAsid() { return regs.dataAsid(); }
185
186 void dumpFuncProfile();
187
188 Fault hwrei();
189
190 bool simPalCheck(int palFunc);
191
192#endif
193
194 /*******************************************
195 * ThreadContext interface functions.
196 ******************************************/
197
198 BaseCPU *getCpuPtr() { return cpu; }
199
200 int getThreadNum() { return tid; }
201
202 TheISA::ITB *getITBPtr() { return itb; }
203
204 TheISA::DTB *getDTBPtr() { return dtb; }
205
206#if FULL_SYSTEM
207 System *getSystemPtr() { return system; }
208
209 FunctionalPort *getPhysPort() { return physPort; }
210
211 /** Return a virtual port. This port cannot be cached locally in an object.
212 * After a CPU switch it may point to the wrong memory object which could
213 * mean stale data.
214 */
215 VirtualPort *getVirtPort() { return virtPort; }
216#endif
217
218 Status status() const { return _status; }
219
220 void setStatus(Status newStatus) { _status = newStatus; }
221
222 /// Set the status to Active. Optional delay indicates number of
223 /// cycles to wait before beginning execution.
224 void activate(int delay = 1);
225
226 /// Set the status to Suspended.
227 void suspend();
228
229 /// Set the status to Unallocated.
230 void deallocate();
231
232 /// Set the status to Halted.
233 void halt();
234
235 virtual bool misspeculating();
236
237 Fault instRead(RequestPtr &req)
238 {
239 panic("instRead not implemented");
240 // return funcPhysMem->read(req, inst);
241 return NoFault;
242 }
243
244 void copyArchRegs(ThreadContext *tc);
245
246 void clearArchRegs() { regs.clear(); }
247
248 //
249 // New accessors for new decoder.
250 //
251 uint64_t readIntReg(int reg_idx)
252 {
253 int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
254 return regs.readIntReg(flatIndex);
255 }
256
257 FloatReg readFloatReg(int reg_idx, int width)
258 {
259 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
260 return regs.readFloatReg(flatIndex, width);
261 }
262
263 FloatReg readFloatReg(int reg_idx)
264 {
265 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
266 return regs.readFloatReg(flatIndex);
267 }
268
269 FloatRegBits readFloatRegBits(int reg_idx, int width)
270 {
271 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
272 return regs.readFloatRegBits(flatIndex, width);
273 }
274
275 FloatRegBits readFloatRegBits(int reg_idx)
276 {
277 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
278 return regs.readFloatRegBits(flatIndex);
279 }
280
281 void setIntReg(int reg_idx, uint64_t val)
282 {
283 int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
284 regs.setIntReg(flatIndex, val);
285 }
286
287 void setFloatReg(int reg_idx, FloatReg val, int width)
288 {
289 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
290 regs.setFloatReg(flatIndex, val, width);
291 }
292
293 void setFloatReg(int reg_idx, FloatReg val)
294 {
295 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
296 regs.setFloatReg(flatIndex, val);
297 }
298
299 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
300 {
301 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
302 regs.setFloatRegBits(flatIndex, val, width);
303 }
304
305 void setFloatRegBits(int reg_idx, FloatRegBits val)
306 {
307 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
308 regs.setFloatRegBits(flatIndex, val);
309 }
310
311 uint64_t readPC()
312 {
313 return regs.readPC();
314 }
315
316 void setPC(uint64_t val)
317 {
318 regs.setPC(val);
319 }
320
321 uint64_t readMicroPC()
322 {
323 return microPC;
324 }
325
326 void setMicroPC(uint64_t val)
327 {
328 microPC = val;
329 }
330
331 uint64_t readNextPC()
332 {
333 return regs.readNextPC();
334 }
335
336 void setNextPC(uint64_t val)
337 {
338 regs.setNextPC(val);
339 }
340
341 uint64_t readNextMicroPC()
342 {
343 return nextMicroPC;
344 }
345
346 void setNextMicroPC(uint64_t val)
347 {
348 nextMicroPC = val;
349 }
350
351 uint64_t readNextNPC()
352 {
353 return regs.readNextNPC();
354 }
355
356 void setNextNPC(uint64_t val)
357 {
358 regs.setNextNPC(val);
359 }
360
361 MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
362 {
363 return regs.readMiscRegNoEffect(misc_reg);
364 }
365
366 MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
367 {
368 return regs.readMiscReg(misc_reg, tc);
369 }
370
371 void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
372 {
373 return regs.setMiscRegNoEffect(misc_reg, val);
374 }
375
376 void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
377 {
378 return regs.setMiscReg(misc_reg, val, tc);
379 }
380
381 unsigned readStCondFailures() { return storeCondFailures; }
382
383 void setStCondFailures(unsigned sc_failures)
384 { storeCondFailures = sc_failures; }
385
386#if !FULL_SYSTEM
387 TheISA::IntReg getSyscallArg(int i)
388 {
389 assert(i < TheISA::NumArgumentRegs);
390 return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
391 TheISA::ArgumentReg[i]));
392 }
393
394 // used to shift args for indirect syscall
395 void setSyscallArg(int i, TheISA::IntReg val)
396 {
397 assert(i < TheISA::NumArgumentRegs);
398 regs.setIntReg(TheISA::flattenIntIndex(getTC(),
399 TheISA::ArgumentReg[i]), val);
400 }
401
402 void setSyscallReturn(SyscallReturn return_value)
403 {
404 TheISA::setSyscallReturn(return_value, getTC());
405 }
406
407 void syscall(int64_t callnum)
408 {
409 process->syscall(callnum, tc);
410 }
411#endif
412};
413
414
415// for non-speculative execution context, spec_mode is always false
416inline bool
417SimpleThread::misspeculating()
418{
419 return false;
420}
421
422#endif // __CPU_CPU_EXEC_CONTEXT_HH__