1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa_traits.hh"
36#include "config/full_system.hh"
37#include "cpu/thread_context.hh"
38#include "cpu/thread_state.hh"
39#include "mem/physical.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/eventq.hh"
43#include "sim/host.hh"
44#include "sim/serialize.hh"
45
46class BaseCPU;
47
48#if FULL_SYSTEM
49
50#include "sim/system.hh"
51#include "arch/tlb.hh"
52
53class FunctionProfile;
54class ProfileNode;
55class FunctionalPort;
56class PhysicalPort;
57
58namespace TheISA {
59 namespace Kernel {
60 class Statistics;
61 };
62};
63
64#else // !FULL_SYSTEM
65
66#include "sim/process.hh"
67#include "mem/page_table.hh"
68class TranslatingPort;
69
70#endif // FULL_SYSTEM
71
72/**
73 * The SimpleThread object provides a combination of the ThreadState
74 * object and the ThreadContext interface. It implements the
75 * ThreadContext interface so that a ProxyThreadContext class can be
76 * made using SimpleThread as the template parameter (see
77 * thread_context.hh). It adds to the ThreadState object by adding all
78 * the objects needed for simple functional execution, including a
79 * simple architectural register file, and pointers to the ITB and DTB
80 * in full system mode. For CPU models that do not need more advanced
81 * ways to hold state (i.e. a separate physical register file, or
82 * separate fetch and commit PC's), this SimpleThread class provides
83 * all the necessary state for full architecture-level functional
84 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
85 * examples.
86 */
87
88class SimpleThread : public ThreadState
89{
90 protected:
91 typedef TheISA::RegFile RegFile;
92 typedef TheISA::MachInst MachInst;
93 typedef TheISA::MiscRegFile MiscRegFile;
94 typedef TheISA::MiscReg MiscReg;
95 typedef TheISA::FloatReg FloatReg;
96 typedef TheISA::FloatRegBits FloatRegBits;
97 public:
98 typedef ThreadContext::Status Status;
99
100 protected:
101 RegFile regs; // correct-path register context
102
103 public:
104 // pointer to CPU associated with this SimpleThread
105 BaseCPU *cpu;
106
107 ProxyThreadContext<SimpleThread> *tc;
108
109 System *system;
110
111#if FULL_SYSTEM
112 TheISA::ITB *itb;
113 TheISA::DTB *dtb;
114#endif
115
116 // constructor: initialize SimpleThread from given process structure
117#if FULL_SYSTEM
118 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
119 TheISA::ITB *_itb, TheISA::DTB *_dtb,
120 bool use_kernel_stats = true);
121
122 void init();
123#else
124 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
125#endif
126
127 SimpleThread();
128
129 virtual ~SimpleThread();
130
131 virtual void takeOverFrom(ThreadContext *oldContext);
132
133 void regStats(const std::string &name);
134
135 void copyTC(ThreadContext *context);
136
137 void copyState(ThreadContext *oldContext);
138
139 void serialize(std::ostream &os);
140 void unserialize(Checkpoint *cp, const std::string &section);
141
142 /***************************************************************
143 * SimpleThread functions to provide CPU with access to various
144 * state, and to provide address translation methods.
145 **************************************************************/
146
147 /** Returns the pointer to this SimpleThread's ThreadContext. Used
148 * when a ThreadContext must be passed to objects outside of the
149 * CPU.
150 */
151 ThreadContext *getTC() { return tc; }
152
153#if FULL_SYSTEM
154 int getInstAsid() { return regs.instAsid(); }
155 int getDataAsid() { return regs.dataAsid(); }
156
157 Fault translateInstReq(RequestPtr &req)
158 {
159 return itb->translate(req, tc);
160 }
161
162 Fault translateDataReadReq(RequestPtr &req)
163 {
164 return dtb->translate(req, tc, false);
165 }
166
167 Fault translateDataWriteReq(RequestPtr &req)
168 {
169 return dtb->translate(req, tc, true);
170 }
171
172 void dumpFuncProfile();
173
174 Fault hwrei();
175
176 bool simPalCheck(int palFunc);
177#else
178
179 Fault translateInstReq(RequestPtr &req)
180 {
181 return process->pTable->translate(req);
182 }
183
184 Fault translateDataReadReq(RequestPtr &req)
185 {
186 return process->pTable->translate(req);
187 }
188
189 Fault translateDataWriteReq(RequestPtr &req)
190 {
191 return process->pTable->translate(req);
192 }
193#endif
194
195 /*******************************************
196 * ThreadContext interface functions.
197 ******************************************/
198
199 BaseCPU *getCpuPtr() { return cpu; }
200
201 int getThreadNum() { return tid; }
202
203#if FULL_SYSTEM
204 System *getSystemPtr() { return system; }
205
206 TheISA::ITB *getITBPtr() { return itb; }
207
208 TheISA::DTB *getDTBPtr() { return dtb; }
209
210 FunctionalPort *getPhysPort() { return physPort; }
211
212 /** Return a virtual port. If no thread context is specified then a static
213 * port is returned. Otherwise a port is created and returned. It must be
214 * deleted by deleteVirtPort(). */
215 VirtualPort *getVirtPort(ThreadContext *tc);
216
217 void delVirtPort(VirtualPort *vp);
218#endif
219
220 Status status() const { return _status; }
221
222 void setStatus(Status newStatus) { _status = newStatus; }
223
224 /// Set the status to Active. Optional delay indicates number of
225 /// cycles to wait before beginning execution.
226 void activate(int delay = 1);
227
228 /// Set the status to Suspended.
229 void suspend();
230
231 /// Set the status to Unallocated.
232 void deallocate();
233
234 /// Set the status to Halted.
235 void halt();
236
237/*
238 template <class T>
239 Fault read(RequestPtr &req, T &data)
240 {
241#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
242 if (req->isLocked()) {
243 req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
244 req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
245 }
246#endif
247
248 Fault error;
249 error = mem->prot_read(req->paddr, data, req->size);
250 data = LittleEndianGuest::gtoh(data);
251 return error;
252 }
253
254 template <class T>
255 Fault write(RequestPtr &req, T &data)
256 {
257#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
258 ExecContext *xc;
259
260 // If this is a store conditional, act appropriately
261 if (req->isLocked()) {
262 xc = req->xc;
263
264 if (req->isUncacheable()) {
265 // Don't update result register (see stq_c in isa_desc)
266 req->result = 2;
267 xc->setStCondFailures(0);//Needed? [RGD]
268 } else {
269 bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
270 Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
271 req->result = lock_flag;
272 if (!lock_flag ||
273 ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
274 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
275 xc->setStCondFailures(xc->readStCondFailures() + 1);
276 if (((xc->readStCondFailures()) % 100000) == 0) {
277 std::cerr << "Warning: "
278 << xc->readStCondFailures()
279 << " consecutive store conditional failures "
280 << "on cpu " << req->xc->readCpuId()
281 << std::endl;
282 }
283 return NoFault;
284 }
285 else xc->setStCondFailures(0);
286 }
287 }
288
289 // Need to clear any locked flags on other proccessors for
290 // this address. Only do this for succsful Store Conditionals
291 // and all other stores (WH64?). Unsuccessful Store
292 // Conditionals would have returned above, and wouldn't fall
293 // through.
294 for (int i = 0; i < system->execContexts.size(); i++){
295 xc = system->execContexts[i];
296 if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
297 (req->paddr & ~0xf)) {
298 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
299 }
300 }
301
302#endif
303 return mem->prot_write(req->paddr, (T)htog(data), req->size);
304 }
305*/
306 virtual bool misspeculating();
307
308 Fault instRead(RequestPtr &req)
309 {
310 panic("instRead not implemented");
311 // return funcPhysMem->read(req, inst);
312 return NoFault;
313 }
314
315 void copyArchRegs(ThreadContext *tc);
316
317 void clearArchRegs() { regs.clear(); }
318
319 //
320 // New accessors for new decoder.
321 //
322 uint64_t readIntReg(int reg_idx)
323 {
324 return regs.readIntReg(reg_idx);
325 }
326
327 FloatReg readFloatReg(int reg_idx, int width)
328 {
329 return regs.readFloatReg(reg_idx, width);
330 }
331
332 FloatReg readFloatReg(int reg_idx)
333 {
334 return regs.readFloatReg(reg_idx);
335 }
336
337 FloatRegBits readFloatRegBits(int reg_idx, int width)
338 {
339 return regs.readFloatRegBits(reg_idx, width);
340 }
341
342 FloatRegBits readFloatRegBits(int reg_idx)
343 {
344 return regs.readFloatRegBits(reg_idx);
345 }
346
347 void setIntReg(int reg_idx, uint64_t val)
348 {
349 regs.setIntReg(reg_idx, val);
350 }
351
352 void setFloatReg(int reg_idx, FloatReg val, int width)
353 {
354 regs.setFloatReg(reg_idx, val, width);
355 }
356
357 void setFloatReg(int reg_idx, FloatReg val)
358 {
359 regs.setFloatReg(reg_idx, val);
360 }
361
362 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
363 {
364 regs.setFloatRegBits(reg_idx, val, width);
365 }
366
367 void setFloatRegBits(int reg_idx, FloatRegBits val)
368 {
369 regs.setFloatRegBits(reg_idx, val);
370 }
371
372 uint64_t readPC()
373 {
374 return regs.readPC();
375 }
376
377 void setPC(uint64_t val)
378 {
379 regs.setPC(val);
380 }
381
382 uint64_t readMicroPC()
383 {
384 return microPC;
385 }
386
387 void setMicroPC(uint64_t val)
388 {
389 microPC = val;
390 }
391
392 uint64_t readNextPC()
393 {
394 return regs.readNextPC();
395 }
396
397 void setNextPC(uint64_t val)
398 {
399 regs.setNextPC(val);
400 }
401
402 uint64_t readNextMicroPC()
403 {
404 return nextMicroPC;
405 }
406
407 void setNextMicroPC(uint64_t val)
408 {
409 nextMicroPC = val;
410 }
411
412 uint64_t readNextNPC()
413 {
414 return regs.readNextNPC();
415 }
416
417 void setNextNPC(uint64_t val)
418 {
419 regs.setNextNPC(val);
420 }
421
422 MiscReg readMiscReg(int misc_reg)
423 {
424 return regs.readMiscReg(misc_reg);
425 }
426
427 MiscReg readMiscRegWithEffect(int misc_reg)
428 {
429 return regs.readMiscRegWithEffect(misc_reg, tc);
430 }
431
432 void setMiscReg(int misc_reg, const MiscReg &val)
433 {
434 return regs.setMiscReg(misc_reg, val);
435 }
436
437 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
438 {
439 return regs.setMiscRegWithEffect(misc_reg, val, tc);
440 }
441
442 unsigned readStCondFailures() { return storeCondFailures; }
443
444 void setStCondFailures(unsigned sc_failures)
445 { storeCondFailures = sc_failures; }
446
447#if !FULL_SYSTEM
448 TheISA::IntReg getSyscallArg(int i)
449 {
450 return regs.readIntReg(TheISA::ArgumentReg0 + i);
451 }
452
453 // used to shift args for indirect syscall
454 void setSyscallArg(int i, TheISA::IntReg val)
455 {
456 regs.setIntReg(TheISA::ArgumentReg0 + i, val);
457 }
458
459 void setSyscallReturn(SyscallReturn return_value)
460 {
461 TheISA::setSyscallReturn(return_value, &regs);
462 }
463
464 void syscall(int64_t callnum)
465 {
466 process->syscall(callnum, tc);
467 }
468#endif
469
470 void changeRegFileContext(TheISA::RegContextParam param,
471 TheISA::RegContextVal val)
472 {
473 regs.changeContext(param, val);
474 }
475};
476
477
478// for non-speculative execution context, spec_mode is always false
479inline bool
480SimpleThread::misspeculating()
481{
482 return false;
483}
484
485#endif // __CPU_CPU_EXEC_CONTEXT_HH__