1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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123 /** The next pc.
124 */
125 Addr nextPC;
126
127 /** The next next pc.
128 */
129 Addr nextNPC;
130
131 public:
132 // pointer to CPU associated with this SimpleThread
133 BaseCPU *cpu;
134
135 ProxyThreadContext<SimpleThread> *tc;
136
137 System *system;
138

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366
367 void setNextNPC(uint64_t val)
368 {
369#if ISA_HAS_DELAY_SLOT
370 nextNPC = val;
371#endif
372 }
373
374 MiscReg
375 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
376 {
377 return isa.readMiscRegNoEffect(misc_reg);
378 }
379
380 MiscReg
381 readMiscReg(int misc_reg, ThreadID tid = 0)

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