1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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94 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
95 * examples.
96 */
97
98class SimpleThread : public ThreadState
99{
100 protected:
101 typedef TheISA::MachInst MachInst;
102 typedef TheISA::MiscReg MiscReg;
103 typedef TheISA::FloatReg FloatReg;
104 typedef TheISA::FloatRegBits FloatRegBits;
105 typedef TheISA::CCReg CCReg;
106 using VecRegContainer = TheISA::VecRegContainer;
107 using VecElem = TheISA::VecElem;
108 public:
109 typedef ThreadContext::Status Status;
110
111 protected:
112 FloatRegBits floatRegs[TheISA::NumFloatRegs];
113 TheISA::IntReg intRegs[TheISA::NumIntRegs];
114 VecRegContainer vecRegs[TheISA::NumVecRegs];
115#ifdef ISA_HAS_CC_REGS
116 TheISA::CCReg ccRegs[TheISA::NumCCRegs];
117#endif
118 TheISA::ISA *const isa; // one "instance" of the current ISA.
119
120 TheISA::PCState _pcState;
121

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235 memset(ccRegs, 0, sizeof(ccRegs));
236#endif
237 isa->clear();
238 }
239
240 //
241 // New accessors for new decoder.
242 //
243 uint64_t readIntReg(int reg_idx)
244 {
245 int flatIndex = isa->flattenIntIndex(reg_idx);
246 assert(flatIndex < TheISA::NumIntRegs);
247 uint64_t regVal(readIntRegFlat(flatIndex));
248 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
249 reg_idx, flatIndex, regVal);
250 return regVal;
251 }
252
253 FloatRegBits readFloatRegBits(int reg_idx)
254 {
255 int flatIndex = isa->flattenFloatIndex(reg_idx);
256 assert(flatIndex < TheISA::NumFloatRegs);
257 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
258 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
259 reg_idx, flatIndex, regVal);
260 return regVal;
261 }
262
263 const VecRegContainer&
264 readVecReg(const RegId& reg) const
265 {

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363 reg_idx, flatIndex, regVal);
364 return regVal;
365#else
366 panic("Tried to read a CC register.");
367 return 0;
368#endif
369 }
370
371 void setIntReg(int reg_idx, uint64_t val)
372 {
373 int flatIndex = isa->flattenIntIndex(reg_idx);
374 assert(flatIndex < TheISA::NumIntRegs);
375 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
376 reg_idx, flatIndex, val);
377 setIntRegFlat(flatIndex, val);
378 }
379
380 void setFloatRegBits(int reg_idx, FloatRegBits val)
381 {
382 int flatIndex = isa->flattenFloatIndex(reg_idx);
383 assert(flatIndex < TheISA::NumFloatRegs);
384 // XXX: Fix array out of bounds compiler error for gem5.fast
385 // when checkercpu enabled
386 if (flatIndex < TheISA::NumFloatRegs)
387 setFloatRegBitsFlat(flatIndex, val);
388 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n",
389 reg_idx, flatIndex, val);
390 }
391
392 void setVecReg(const RegId& reg, const VecRegContainer& val)
393 {
394 int flatIndex = isa->flattenVecIndex(reg.index());
395 assert(flatIndex < TheISA::NumVecRegs);
396 setVecRegFlat(flatIndex, val);
397 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n",
398 reg.index(), flatIndex, val.print());
399 }
400
401 void setVecElem(const RegId& reg, const VecElem& val)
402 {
403 int flatIndex = isa->flattenVecElemIndex(reg.index());
404 assert(flatIndex < TheISA::NumVecRegs);
405 setVecElemFlat(flatIndex, reg.elemIndex(), val);
406 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to"
407 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
408 }
409
410 void setCCReg(int reg_idx, CCReg val)
411 {
412#ifdef ISA_HAS_CC_REGS
413 int flatIndex = isa->flattenCCIndex(reg_idx);
414 assert(flatIndex < TheISA::NumCCRegs);
415 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
416 reg_idx, flatIndex, val);
417 setCCRegFlat(flatIndex, val);
418#else

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467 return predicate;
468 }
469
470 void setPredicate(bool val)
471 {
472 predicate = val;
473 }
474
475 MiscReg
476 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
477 {
478 return isa->readMiscRegNoEffect(misc_reg);
479 }
480
481 MiscReg
482 readMiscReg(int misc_reg, ThreadID tid = 0)
483 {
484 return isa->readMiscReg(misc_reg, tc);
485 }
486
487 void
488 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
489 {
490 return isa->setMiscRegNoEffect(misc_reg, val);
491 }
492
493 void
494 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
495 {
496 return isa->setMiscReg(misc_reg, val, tc);
497 }
498
499 RegId
500 flattenRegId(const RegId& regId) const
501 {
502 return isa->flattenRegId(regId);
503 }
504
505 unsigned readStCondFailures() { return storeCondFailures; }
506
507 void setStCondFailures(unsigned sc_failures)
508 { storeCondFailures = sc_failures; }
509
510 void syscall(int64_t callnum, Fault *fault)
511 {
512 process->syscall(callnum, tc, fault);
513 }
514
515 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
516 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
517
518 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs[idx]; }
519 void setFloatRegBitsFlat(int idx, FloatRegBits val) {
520 floatRegs[idx] = val;
521 }
522
523 const VecRegContainer& readVecRegFlat(const RegIndex& reg) const
524 {
525 return vecRegs[reg];
526 }
527
528 VecRegContainer& getWritableVecRegFlat(const RegIndex& reg)
529 {
530 return vecRegs[reg];
531 }
532
533 void setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
534 {
535 vecRegs[reg] = val;
536 }
537
538 template <typename T>
539 VecLaneT<T, true> readVecLaneFlat(const RegIndex& reg, int lId) const
540 {
541 return vecRegs[reg].laneView<T>(lId);
542 }
543
544 template <typename LD>
545 void setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
546 {
547 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
548 }
549
550 const VecElem& readVecElemFlat(const RegIndex& reg,
551 const ElemIndex& elemIndex) const
552 {
553 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
554 }
555
556 void setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
557 const VecElem val)
558 {
559 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
560 }
561
562#ifdef ISA_HAS_CC_REGS
563 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
564 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
565#else
566 CCReg readCCRegFlat(int idx)
567 { panic("readCCRegFlat w/no CC regs!\n"); }
568
569 void setCCRegFlat(int idx, CCReg val)
570 { panic("setCCRegFlat w/no CC regs!\n"); }
571#endif
572};
573
574
575#endif // __CPU_CPU_EXEC_CONTEXT_HH__