1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa.hh"
36#include "arch/isa_traits.hh"
37#include "arch/regfile.hh"
38#include "arch/tlb.hh"
39#include "arch/types.hh"
40#include "base/types.hh"
41#include "config/full_system.hh"
42#include "cpu/thread_context.hh"
43#include "cpu/thread_state.hh"
44#include "mem/request.hh"
45#include "sim/byteswap.hh"
46#include "sim/eventq.hh"
47#include "sim/serialize.hh"
48
49class BaseCPU;
50
51#if FULL_SYSTEM
52
53#include "sim/system.hh"
54
55class FunctionProfile;
56class ProfileNode;
57class FunctionalPort;
58class PhysicalPort;
59
60namespace TheISA {
61 namespace Kernel {
62 class Statistics;
63 };
64};
65
66#else // !FULL_SYSTEM
67
68#include "sim/process.hh"
69#include "mem/page_table.hh"
70class TranslatingPort;
71
72#endif // FULL_SYSTEM
73
74/**
75 * The SimpleThread object provides a combination of the ThreadState
76 * object and the ThreadContext interface. It implements the
77 * ThreadContext interface so that a ProxyThreadContext class can be
78 * made using SimpleThread as the template parameter (see
79 * thread_context.hh). It adds to the ThreadState object by adding all
80 * the objects needed for simple functional execution, including a
81 * simple architectural register file, and pointers to the ITB and DTB
82 * in full system mode. For CPU models that do not need more advanced
83 * ways to hold state (i.e. a separate physical register file, or
84 * separate fetch and commit PC's), this SimpleThread class provides
85 * all the necessary state for full architecture-level functional
86 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
87 * examples.
88 */
89
90class SimpleThread : public ThreadState
91{
92 protected:
93 typedef TheISA::RegFile RegFile;
94 typedef TheISA::MachInst MachInst;
95 typedef TheISA::MiscReg MiscReg;
96 typedef TheISA::FloatReg FloatReg;
97 typedef TheISA::FloatRegBits FloatRegBits;
98 public:
99 typedef ThreadContext::Status Status;
100
101 protected:
102 RegFile regs; // correct-path register context
103 union {
104 FloatReg f[TheISA::NumFloatRegs];
105 FloatRegBits i[TheISA::NumFloatRegs];
106 } floatRegs;
107 TheISA::IntReg intRegs[TheISA::NumIntRegs];
108 TheISA::ISA isa; // one "instance" of the current ISA.
109
110 public:
111 // pointer to CPU associated with this SimpleThread
112 BaseCPU *cpu;
113
114 ProxyThreadContext<SimpleThread> *tc;
115
116 System *system;
117
118 TheISA::TLB *itb;
119 TheISA::TLB *dtb;
120
121 // constructor: initialize SimpleThread from given process structure
122#if FULL_SYSTEM
123 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
124 TheISA::TLB *_itb, TheISA::TLB *_dtb,
125 bool use_kernel_stats = true);
126#else
127 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
128 TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid);
129#endif
130
131 SimpleThread();
132
133 virtual ~SimpleThread();
134
135 virtual void takeOverFrom(ThreadContext *oldContext);
136
137 void regStats(const std::string &name);
138
139 void copyTC(ThreadContext *context);
140
141 void copyState(ThreadContext *oldContext);
142
143 void serialize(std::ostream &os);
144 void unserialize(Checkpoint *cp, const std::string &section);
145
146 /***************************************************************
147 * SimpleThread functions to provide CPU with access to various
148 * state.
149 **************************************************************/
150
151 /** Returns the pointer to this SimpleThread's ThreadContext. Used
152 * when a ThreadContext must be passed to objects outside of the
153 * CPU.
154 */
155 ThreadContext *getTC() { return tc; }
156
157 void demapPage(Addr vaddr, uint64_t asn)
158 {
159 itb->demapPage(vaddr, asn);
160 dtb->demapPage(vaddr, asn);
161 }
162
163 void demapInstPage(Addr vaddr, uint64_t asn)
164 {
165 itb->demapPage(vaddr, asn);
166 }
167
168 void demapDataPage(Addr vaddr, uint64_t asn)
169 {
170 dtb->demapPage(vaddr, asn);
171 }
172
173#if FULL_SYSTEM
174 int getInstAsid() { return isa.instAsid(); }
175 int getDataAsid() { return isa.dataAsid(); }
176
177 void dumpFuncProfile();
178
179 Fault hwrei();
180
181 bool simPalCheck(int palFunc);
182
183#endif
184
185 /*******************************************
186 * ThreadContext interface functions.
187 ******************************************/
188
189 BaseCPU *getCpuPtr() { return cpu; }
190
191 TheISA::TLB *getITBPtr() { return itb; }
192
193 TheISA::TLB *getDTBPtr() { return dtb; }
194
195 System *getSystemPtr() { return system; }
196
197#if FULL_SYSTEM
198 FunctionalPort *getPhysPort() { return physPort; }
199
200 /** Return a virtual port. This port cannot be cached locally in an object.
201 * After a CPU switch it may point to the wrong memory object which could
202 * mean stale data.
203 */
204 VirtualPort *getVirtPort() { return virtPort; }
205#endif
206
207 Status status() const { return _status; }
208
209 void setStatus(Status newStatus) { _status = newStatus; }
210
211 /// Set the status to Active. Optional delay indicates number of
212 /// cycles to wait before beginning execution.
213 void activate(int delay = 1);
214
215 /// Set the status to Suspended.
216 void suspend();
217
218 /// Set the status to Halted.
219 void halt();
220
221 virtual bool misspeculating();
222
223 Fault instRead(RequestPtr &req)
224 {
225 panic("instRead not implemented");
226 // return funcPhysMem->read(req, inst);
227 return NoFault;
228 }
229
230 void copyArchRegs(ThreadContext *tc);
231
232 void clearArchRegs()
233 {
234 regs.clear();
235 memset(intRegs, 0, sizeof(intRegs));
236 memset(floatRegs.i, 0, sizeof(floatRegs.i));
237 }
238
239 //
240 // New accessors for new decoder.
241 //
242 uint64_t readIntReg(int reg_idx)
243 {
244 int flatIndex = isa.flattenIntIndex(reg_idx);
245 return intRegs[flatIndex];
246 }
247
248 FloatReg readFloatReg(int reg_idx)
249 {
250 int flatIndex = isa.flattenFloatIndex(reg_idx);
251 return floatRegs.f[flatIndex];
252 }
253
254 FloatRegBits readFloatRegBits(int reg_idx)
255 {
256 int flatIndex = isa.flattenFloatIndex(reg_idx);
257 return floatRegs.i[flatIndex];
258 }
259
260 void setIntReg(int reg_idx, uint64_t val)
261 {
262 int flatIndex = isa.flattenIntIndex(reg_idx);
263 intRegs[flatIndex] = val;
264 }
265
266 void setFloatReg(int reg_idx, FloatReg val)
267 {
268 int flatIndex = isa.flattenFloatIndex(reg_idx);
269 floatRegs.f[flatIndex] = val;
270 }
271
272 void setFloatRegBits(int reg_idx, FloatRegBits val)
273 {
274 int flatIndex = isa.flattenFloatIndex(reg_idx);
275 floatRegs.i[flatIndex] = val;
276 }
277
278 uint64_t readPC()
279 {
280 return regs.readPC();
281 }
282
283 void setPC(uint64_t val)
284 {
285 regs.setPC(val);
286 }
287
288 uint64_t readMicroPC()
289 {
290 return microPC;
291 }
292
293 void setMicroPC(uint64_t val)
294 {
295 microPC = val;
296 }
297
298 uint64_t readNextPC()
299 {
300 return regs.readNextPC();
301 }
302
303 void setNextPC(uint64_t val)
304 {
305 regs.setNextPC(val);
306 }
307
308 uint64_t readNextMicroPC()
309 {
310 return nextMicroPC;
311 }
312
313 void setNextMicroPC(uint64_t val)
314 {
315 nextMicroPC = val;
316 }
317
318 uint64_t readNextNPC()
319 {
320 return regs.readNextNPC();
321 }
322
323 void setNextNPC(uint64_t val)
324 {
325 regs.setNextNPC(val);
326 }
327
328 MiscReg
329 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
330 {
331 return isa.readMiscRegNoEffect(misc_reg);
332 }
333
334 MiscReg
335 readMiscReg(int misc_reg, ThreadID tid = 0)
336 {
337 return isa.readMiscReg(misc_reg, tc);
338 }
339
340 void
341 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
342 {
343 return isa.setMiscRegNoEffect(misc_reg, val);
344 }
345
346 void
347 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
348 {
349 return isa.setMiscReg(misc_reg, val, tc);
350 }
351
352 int
353 flattenIntIndex(int reg)
354 {
355 return isa.flattenIntIndex(reg);
356 }
357
358 int
359 flattenFloatIndex(int reg)
360 {
361 return isa.flattenFloatIndex(reg);
362 }
363
364 unsigned readStCondFailures() { return storeCondFailures; }
365
366 void setStCondFailures(unsigned sc_failures)
367 { storeCondFailures = sc_failures; }
368
369#if !FULL_SYSTEM
370 void syscall(int64_t callnum)
371 {
372 process->syscall(callnum, tc);
373 }
374#endif
375};
376
377
378// for non-speculative execution context, spec_mode is always false
379inline bool
380SimpleThread::misspeculating()
381{
382 return false;
383}
384
385#endif // __CPU_CPU_EXEC_CONTEXT_HH__