1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2001-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 */
44
45#ifndef __CPU_SIMPLE_THREAD_HH__
46#define __CPU_SIMPLE_THREAD_HH__
47
48#include "arch/decoder.hh"
49#include "arch/generic/tlb.hh"
50#include "arch/isa.hh"
51#include "arch/isa_traits.hh"
52#include "arch/registers.hh"
53#include "arch/types.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/thread_context.hh"
57#include "cpu/thread_state.hh"
58#include "debug/CCRegs.hh"
59#include "debug/FloatRegs.hh"
60#include "debug/IntRegs.hh"
61#include "debug/VecPredRegs.hh"
62#include "debug/VecRegs.hh"
63#include "mem/page_table.hh"
64#include "mem/request.hh"
65#include "sim/byteswap.hh"
66#include "sim/eventq.hh"
67#include "sim/process.hh"
68#include "sim/serialize.hh"
69#include "sim/system.hh"
70
71class BaseCPU;
72class CheckerCPU;
73
74class FunctionProfile;
75class ProfileNode;
76
77namespace Kernel {
78 class Statistics;
79}
80
81/**
82 * The SimpleThread object provides a combination of the ThreadState
83 * object and the ThreadContext interface. It implements the
84 * ThreadContext interface and adds to the ThreadState object by adding all
85 * the objects needed for simple functional execution, including a
86 * simple architectural register file, and pointers to the ITB and DTB
87 * in full system mode. For CPU models that do not need more advanced
88 * ways to hold state (i.e. a separate physical register file, or
89 * separate fetch and commit PC's), this SimpleThread class provides
90 * all the necessary state for full architecture-level functional
91 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
92 * examples.
93 */
94
95class SimpleThread : public ThreadState, public ThreadContext
96{
97 protected:
98 typedef TheISA::MachInst MachInst;
99 using VecRegContainer = TheISA::VecRegContainer;
100 using VecElem = TheISA::VecElem;
101 using VecPredRegContainer = TheISA::VecPredRegContainer;
102 public:
103 typedef ThreadContext::Status Status;
104
105 protected:
106 RegVal floatRegs[TheISA::NumFloatRegs];
107 RegVal intRegs[TheISA::NumIntRegs];
108 VecRegContainer vecRegs[TheISA::NumVecRegs];
109 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
110#ifdef ISA_HAS_CC_REGS
111 RegVal ccRegs[TheISA::NumCCRegs];
112#endif
113 TheISA::ISA *const isa; // one "instance" of the current ISA.
114
115 TheISA::PCState _pcState;
116
117 /** Did this instruction execute or is it predicated false */
118 bool predicate;
119
120 /** True if the memory access should be skipped for this instruction */
121 bool memAccPredicate;
122
123 public:
124 std::string name() const
125 {
126 return csprintf("%s.[tid:%i]", baseCpu->name(), threadId());
127 }
128
129 System *system;
130
131 BaseTLB *itb;
132 BaseTLB *dtb;
133
134 TheISA::Decoder decoder;
135
136 // constructor: initialize SimpleThread from given process structure
137 // FS
138 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
139 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa,
140 bool use_kernel_stats = true);
141 // SE
142 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
143 Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
144 TheISA::ISA *_isa);
145
146 virtual ~SimpleThread() {}
147
148 void takeOverFrom(ThreadContext *oldContext) override;
149
150 void regStats(const std::string &name) override;
151
152 void copyState(ThreadContext *oldContext);
153
154 void serialize(CheckpointOut &cp) const override;
155 void unserialize(CheckpointIn &cp) override;
156 void startup();
157
158 /***************************************************************
159 * SimpleThread functions to provide CPU with access to various
160 * state.
161 **************************************************************/
162
163 /** Returns the pointer to this SimpleThread's ThreadContext. Used
164 * when a ThreadContext must be passed to objects outside of the
165 * CPU.
166 */
167 ThreadContext *getTC() { return this; }
168
169 void demapPage(Addr vaddr, uint64_t asn)
170 {
171 itb->demapPage(vaddr, asn);
172 dtb->demapPage(vaddr, asn);
173 }
174
175 void demapInstPage(Addr vaddr, uint64_t asn)
176 {
177 itb->demapPage(vaddr, asn);
178 }
179
180 void demapDataPage(Addr vaddr, uint64_t asn)
181 {
182 dtb->demapPage(vaddr, asn);
183 }
184
185 void dumpFuncProfile() override;
186
187 /*******************************************
188 * ThreadContext interface functions.
189 ******************************************/
190
191 BaseCPU *getCpuPtr() override { return baseCpu; }
192
193 int cpuId() const override { return ThreadState::cpuId(); }
194 uint32_t socketId() const override { return ThreadState::socketId(); }
195 int threadId() const override { return ThreadState::threadId(); }
196 void setThreadId(int id) override { ThreadState::setThreadId(id); }
197 ContextID contextId() const override { return ThreadState::contextId(); }
198 void setContextId(ContextID id) override { ThreadState::setContextId(id); }
199
200 BaseTLB *getITBPtr() override { return itb; }
201
202 BaseTLB *getDTBPtr() override { return dtb; }
203
204 CheckerCPU *getCheckerCpuPtr() override { return NULL; }
205
206 TheISA::ISA *getIsaPtr() override { return isa; }
207
208 TheISA::Decoder *getDecoderPtr() override { return &decoder; }
209
210 System *getSystemPtr() override { return system; }
211
212 Kernel::Statistics *
213 getKernelStats() override
214 {
215 return ThreadState::getKernelStats();
216 }
217
218 PortProxy &getPhysProxy() override { return ThreadState::getPhysProxy(); }
219 PortProxy &getVirtProxy() override { return ThreadState::getVirtProxy(); }
220
221 void initMemProxies(ThreadContext *tc) override
222 {
223 ThreadState::initMemProxies(tc);
224 }
225
226 Process *getProcessPtr() override { return ThreadState::getProcessPtr(); }
227 void setProcessPtr(Process *p) override { ThreadState::setProcessPtr(p); }
228
229 Status status() const override { return _status; }
230
231 void setStatus(Status newStatus) override { _status = newStatus; }
232
233 /// Set the status to Active.
234 void activate() override;
235
236 /// Set the status to Suspended.
237 void suspend() override;
238
239 /// Set the status to Halted.
240 void halt() override;
241
242 EndQuiesceEvent *
243 getQuiesceEvent() override
244 {
245 return ThreadState::getQuiesceEvent();
246 }
247
248 Tick
249 readLastActivate() override
250 {
251 return ThreadState::readLastActivate();
252 }
253 Tick
254 readLastSuspend() override
255 {
256 return ThreadState::readLastSuspend();
257 }
258
259 void profileClear() override { ThreadState::profileClear(); }
260 void profileSample() override { ThreadState::profileSample(); }
261
262 void copyArchRegs(ThreadContext *tc) override;
263
264 void clearArchRegs() override
265 {
266 _pcState = 0;
267 memset(intRegs, 0, sizeof(intRegs));
268 memset(floatRegs, 0, sizeof(floatRegs));
269 for (int i = 0; i < TheISA::NumVecRegs; i++) {
270 vecRegs[i].zero();
271 }
272 for (int i = 0; i < TheISA::NumVecPredRegs; i++) {
273 vecPredRegs[i].reset();
274 }
275#ifdef ISA_HAS_CC_REGS
276 memset(ccRegs, 0, sizeof(ccRegs));
277#endif
278 isa->clear();
279 }
280
281 //
282 // New accessors for new decoder.
283 //
284 RegVal
285 readIntReg(RegIndex reg_idx) const override
286 {
287 int flatIndex = isa->flattenIntIndex(reg_idx);
288 assert(flatIndex < TheISA::NumIntRegs);
289 uint64_t regVal(readIntRegFlat(flatIndex));
290 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
291 reg_idx, flatIndex, regVal);
292 return regVal;
293 }
294
295 RegVal
296 readFloatReg(RegIndex reg_idx) const override
297 {
298 int flatIndex = isa->flattenFloatIndex(reg_idx);
299 assert(flatIndex < TheISA::NumFloatRegs);
300 RegVal regVal(readFloatRegFlat(flatIndex));
301 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
302 reg_idx, flatIndex, regVal);
303 return regVal;
304 }
305
306 const VecRegContainer&
307 readVecReg(const RegId& reg) const override
308 {
309 int flatIndex = isa->flattenVecIndex(reg.index());
310 assert(flatIndex < TheISA::NumVecRegs);
311 const VecRegContainer& regVal = readVecRegFlat(flatIndex);
312 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
313 reg.index(), flatIndex, regVal.print());
314 return regVal;
315 }
316
317 VecRegContainer&
318 getWritableVecReg(const RegId& reg) override
319 {
320 int flatIndex = isa->flattenVecIndex(reg.index());
321 assert(flatIndex < TheISA::NumVecRegs);
322 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
323 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
324 reg.index(), flatIndex, regVal.print());
325 return regVal;
326 }
327
328 /** Vector Register Lane Interfaces. */
329 /** @{ */
330 /** Reads source vector <T> operand. */
331 template <typename T>
332 VecLaneT<T, true>
333 readVecLane(const RegId& reg) const
334 {
335 int flatIndex = isa->flattenVecIndex(reg.index());
336 assert(flatIndex < TheISA::NumVecRegs);
337 auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex());
338 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n",
339 reg.index(), flatIndex, reg.elemIndex(), regVal);
340 return regVal;
341 }
342
343 /** Reads source vector 8bit operand. */
344 virtual ConstVecLane8
345 readVec8BitLaneReg(const RegId &reg) const override
346 {
347 return readVecLane<uint8_t>(reg);
348 }
349
350 /** Reads source vector 16bit operand. */
351 virtual ConstVecLane16
352 readVec16BitLaneReg(const RegId &reg) const override
353 {
354 return readVecLane<uint16_t>(reg);
355 }
356
357 /** Reads source vector 32bit operand. */
358 virtual ConstVecLane32
359 readVec32BitLaneReg(const RegId &reg) const override
360 {
361 return readVecLane<uint32_t>(reg);
362 }
363
364 /** Reads source vector 64bit operand. */
365 virtual ConstVecLane64
366 readVec64BitLaneReg(const RegId &reg) const override
367 {
368 return readVecLane<uint64_t>(reg);
369 }
370
371 /** Write a lane of the destination vector register. */
372 template <typename LD>
373 void
374 setVecLaneT(const RegId &reg, const LD &val)
375 {
376 int flatIndex = isa->flattenVecIndex(reg.index());
377 assert(flatIndex < TheISA::NumVecRegs);
378 setVecLaneFlat(flatIndex, reg.elemIndex(), val);
379 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n",
380 reg.index(), flatIndex, reg.elemIndex(), val);
381 }
382 virtual void
383 setVecLane(const RegId &reg, const LaneData<LaneSize::Byte> &val) override
384 {
385 return setVecLaneT(reg, val);
386 }
387 virtual void
388 setVecLane(const RegId &reg,
389 const LaneData<LaneSize::TwoByte> &val) override
390 {
391 return setVecLaneT(reg, val);
392 }
393 virtual void
394 setVecLane(const RegId &reg,
395 const LaneData<LaneSize::FourByte> &val) override
396 {
397 return setVecLaneT(reg, val);
398 }
399 virtual void
400 setVecLane(const RegId &reg,
401 const LaneData<LaneSize::EightByte> &val) override
402 {
403 return setVecLaneT(reg, val);
404 }
405 /** @} */
406
407 const VecElem &
408 readVecElem(const RegId &reg) const override
409 {
410 int flatIndex = isa->flattenVecElemIndex(reg.index());
411 assert(flatIndex < TheISA::NumVecRegs);
412 const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex());
413 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
414 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
415 return regVal;
416 }
417
418 const VecPredRegContainer &
419 readVecPredReg(const RegId &reg) const override
420 {
421 int flatIndex = isa->flattenVecPredIndex(reg.index());
422 assert(flatIndex < TheISA::NumVecPredRegs);
423 const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex);
424 DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
425 reg.index(), flatIndex, regVal.print());
426 return regVal;
427 }
428
429 VecPredRegContainer &
430 getWritableVecPredReg(const RegId &reg) override
431 {
432 int flatIndex = isa->flattenVecPredIndex(reg.index());
433 assert(flatIndex < TheISA::NumVecPredRegs);
434 VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex);
435 DPRINTF(VecPredRegs,
436 "Reading predicate reg %d (%d) as %s for modify.\n",
437 reg.index(), flatIndex, regVal.print());
438 return regVal;
439 }
440
441 RegVal
442 readCCReg(RegIndex reg_idx) const override
443 {
444#ifdef ISA_HAS_CC_REGS
445 int flatIndex = isa->flattenCCIndex(reg_idx);
446 assert(0 <= flatIndex);
447 assert(flatIndex < TheISA::NumCCRegs);
448 uint64_t regVal(readCCRegFlat(flatIndex));
449 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
450 reg_idx, flatIndex, regVal);
451 return regVal;
452#else
453 panic("Tried to read a CC register.");
454 return 0;
455#endif
456 }
457
458 void
459 setIntReg(RegIndex reg_idx, RegVal val) override
460 {
461 int flatIndex = isa->flattenIntIndex(reg_idx);
462 assert(flatIndex < TheISA::NumIntRegs);
463 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
464 reg_idx, flatIndex, val);
465 setIntRegFlat(flatIndex, val);
466 }
467
468 void
469 setFloatReg(RegIndex reg_idx, RegVal val) override
470 {
471 int flatIndex = isa->flattenFloatIndex(reg_idx);
472 assert(flatIndex < TheISA::NumFloatRegs);
473 // XXX: Fix array out of bounds compiler error for gem5.fast
474 // when checkercpu enabled
475 if (flatIndex < TheISA::NumFloatRegs)
476 setFloatRegFlat(flatIndex, val);
477 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n",
478 reg_idx, flatIndex, val);
479 }
480
481 void
482 setVecReg(const RegId &reg, const VecRegContainer &val) override
483 {
484 int flatIndex = isa->flattenVecIndex(reg.index());
485 assert(flatIndex < TheISA::NumVecRegs);
486 setVecRegFlat(flatIndex, val);
487 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n",
488 reg.index(), flatIndex, val.print());
489 }
490
491 void
492 setVecElem(const RegId &reg, const VecElem &val) override
493 {
494 int flatIndex = isa->flattenVecElemIndex(reg.index());
495 assert(flatIndex < TheISA::NumVecRegs);
496 setVecElemFlat(flatIndex, reg.elemIndex(), val);
497 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to"
498 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
499 }
500
501 void
502 setVecPredReg(const RegId &reg, const VecPredRegContainer &val) override
503 {
504 int flatIndex = isa->flattenVecPredIndex(reg.index());
505 assert(flatIndex < TheISA::NumVecPredRegs);
506 setVecPredRegFlat(flatIndex, val);
507 DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
508 reg.index(), flatIndex, val.print());
509 }
510
511 void
512 setCCReg(RegIndex reg_idx, RegVal val) override
513 {
514#ifdef ISA_HAS_CC_REGS
515 int flatIndex = isa->flattenCCIndex(reg_idx);
516 assert(flatIndex < TheISA::NumCCRegs);
517 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
518 reg_idx, flatIndex, val);
519 setCCRegFlat(flatIndex, val);
520#else
521 panic("Tried to set a CC register.");
522#endif
523 }
524
525 TheISA::PCState pcState() const override { return _pcState; }
526 void pcState(const TheISA::PCState &val) override { _pcState = val; }
527
528 void
529 pcStateNoRecord(const TheISA::PCState &val) override
530 {
531 _pcState = val;
532 }
533
534 Addr instAddr() const override { return _pcState.instAddr(); }
535 Addr nextInstAddr() const override { return _pcState.nextInstAddr(); }
536 MicroPC microPC() const override { return _pcState.microPC(); }
537 bool readPredicate() const { return predicate; }
538 void setPredicate(bool val) { predicate = val; }
539
540 RegVal
541 readMiscRegNoEffect(RegIndex misc_reg) const override
542 {
543 return isa->readMiscRegNoEffect(misc_reg);
544 }
545
546 RegVal
547 readMiscReg(RegIndex misc_reg) override
548 {
549 return isa->readMiscReg(misc_reg, this);
550 }
551
552 void
553 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
554 {
555 return isa->setMiscRegNoEffect(misc_reg, val);
556 }
557
558 void
559 setMiscReg(RegIndex misc_reg, RegVal val) override
560 {
561 return isa->setMiscReg(misc_reg, val, this);
562 }
563
564 RegId
565 flattenRegId(const RegId& regId) const override
566 {
567 return isa->flattenRegId(regId);
568 }
569
570 unsigned readStCondFailures() const override { return storeCondFailures; }
571
572 bool
573 readMemAccPredicate()
574 {
575 return memAccPredicate;
576 }
577
578 void
579 setMemAccPredicate(bool val)
580 {
581 memAccPredicate = val;
582 }
583
584 void
585 setStCondFailures(unsigned sc_failures) override
586 {
587 storeCondFailures = sc_failures;
588 }
589
590 Counter
591 readFuncExeInst() const override
592 {
593 return ThreadState::readFuncExeInst();
594 }
595
596 void
597 syscall(int64_t callnum, Fault *fault) override
598 {
599 process->syscall(callnum, this, fault);
600 }
601
602 RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; }
603 void
604 setIntRegFlat(RegIndex idx, RegVal val) override
605 {
606 intRegs[idx] = val;
607 }
608
609 RegVal
610 readFloatRegFlat(RegIndex idx) const override
611 {
612 return floatRegs[idx];
613 }
614 void
615 setFloatRegFlat(RegIndex idx, RegVal val) override
616 {
617 floatRegs[idx] = val;
618 }
619
620 const VecRegContainer &
621 readVecRegFlat(RegIndex reg) const override
622 {
623 return vecRegs[reg];
624 }
625
626 VecRegContainer &
627 getWritableVecRegFlat(RegIndex reg) override
628 {
629 return vecRegs[reg];
630 }
631
632 void
633 setVecRegFlat(RegIndex reg, const VecRegContainer &val) override
634 {
635 vecRegs[reg] = val;
636 }
637
638 template <typename T>
639 VecLaneT<T, true>
640 readVecLaneFlat(RegIndex reg, int lId) const
641 {
642 return vecRegs[reg].laneView<T>(lId);
643 }
644
645 template <typename LD>
646 void
647 setVecLaneFlat(RegIndex reg, int lId, const LD &val)
648 {
649 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
650 }
651
652 const VecElem &
653 readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
654 {
655 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
656 }
657
658 void
659 setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
660 const VecElem &val) override
661 {
662 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
663 }
664
665 const VecPredRegContainer &
666 readVecPredRegFlat(RegIndex reg) const override
667 {
668 return vecPredRegs[reg];
669 }
670
671 VecPredRegContainer &
672 getWritableVecPredRegFlat(RegIndex reg) override
673 {
674 return vecPredRegs[reg];
675 }
676
677 void
678 setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override
679 {
680 vecPredRegs[reg] = val;
681 }
682
683#ifdef ISA_HAS_CC_REGS
684 RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
685 void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; }
686#else
687 RegVal
688 readCCRegFlat(RegIndex idx) const override
689 {
690 panic("readCCRegFlat w/no CC regs!\n");
691 }
692
693 void
694 setCCRegFlat(RegIndex idx, RegVal val) override
695 {
696 panic("setCCRegFlat w/no CC regs!\n");
697 }
698#endif
699};
700
701
702#endif // __CPU_CPU_EXEC_CONTEXT_HH__