1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2001-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 */
44
45#ifndef __CPU_SIMPLE_THREAD_HH__
46#define __CPU_SIMPLE_THREAD_HH__
47
48#include "arch/decoder.hh"
49#include "arch/generic/tlb.hh"
50#include "arch/isa.hh"
51#include "arch/isa_traits.hh"
52#include "arch/registers.hh"
53#include "arch/types.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/thread_context.hh"
57#include "cpu/thread_state.hh"
58#include "debug/CCRegs.hh"
59#include "debug/FloatRegs.hh"
60#include "debug/IntRegs.hh"
61#include "debug/VecRegs.hh"
62#include "mem/page_table.hh"
63#include "mem/request.hh"
64#include "sim/byteswap.hh"
65#include "sim/eventq.hh"
66#include "sim/process.hh"
67#include "sim/serialize.hh"
68#include "sim/system.hh"
69
70class BaseCPU;
71class CheckerCPU;
72
73class FunctionProfile;
74class ProfileNode;
75
76namespace TheISA {
77 namespace Kernel {
78 class Statistics;
79 }
80}
81
82/**
83 * The SimpleThread object provides a combination of the ThreadState
84 * object and the ThreadContext interface. It implements the
85 * ThreadContext interface so that a ProxyThreadContext class can be
86 * made using SimpleThread as the template parameter (see
87 * thread_context.hh). It adds to the ThreadState object by adding all
88 * the objects needed for simple functional execution, including a
89 * simple architectural register file, and pointers to the ITB and DTB
90 * in full system mode. For CPU models that do not need more advanced
91 * ways to hold state (i.e. a separate physical register file, or
92 * separate fetch and commit PC's), this SimpleThread class provides
93 * all the necessary state for full architecture-level functional
94 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
95 * examples.
96 */
97
98class SimpleThread : public ThreadState
99{
100 protected:
101 typedef TheISA::MachInst MachInst;
102 typedef TheISA::CCReg CCReg;
103 using VecRegContainer = TheISA::VecRegContainer;
104 using VecElem = TheISA::VecElem;
105 public:
106 typedef ThreadContext::Status Status;
107
108 protected:
109 RegVal floatRegs[TheISA::NumFloatRegs];
110 RegVal intRegs[TheISA::NumIntRegs];
111 VecRegContainer vecRegs[TheISA::NumVecRegs];
112#ifdef ISA_HAS_CC_REGS
113 TheISA::CCReg ccRegs[TheISA::NumCCRegs];
114#endif
115 TheISA::ISA *const isa; // one "instance" of the current ISA.
116
117 TheISA::PCState _pcState;
118
119 /** Did this instruction execute or is it predicated false */
120 bool predicate;
121
122 public:
123 std::string name() const
124 {
125 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
126 }
127
128 ProxyThreadContext<SimpleThread> *tc;
129
130 System *system;
131
132 BaseTLB *itb;
133 BaseTLB *dtb;
134
135 TheISA::Decoder decoder;
136
137 // constructor: initialize SimpleThread from given process structure
138 // FS
139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
140 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa,
141 bool use_kernel_stats = true);
142 // SE
143 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
144 Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
145 TheISA::ISA *_isa);
146
147 virtual ~SimpleThread();
148
149 virtual void takeOverFrom(ThreadContext *oldContext);
150
151 void regStats(const std::string &name);
152
153 void copyState(ThreadContext *oldContext);
154
155 void serialize(CheckpointOut &cp) const override;
156 void unserialize(CheckpointIn &cp) override;
157 void startup();
158
159 /***************************************************************
160 * SimpleThread functions to provide CPU with access to various
161 * state.
162 **************************************************************/
163
164 /** Returns the pointer to this SimpleThread's ThreadContext. Used
165 * when a ThreadContext must be passed to objects outside of the
166 * CPU.
167 */
168 ThreadContext *getTC() { return tc; }
169
170 void demapPage(Addr vaddr, uint64_t asn)
171 {
172 itb->demapPage(vaddr, asn);
173 dtb->demapPage(vaddr, asn);
174 }
175
176 void demapInstPage(Addr vaddr, uint64_t asn)
177 {
178 itb->demapPage(vaddr, asn);
179 }
180
181 void demapDataPage(Addr vaddr, uint64_t asn)
182 {
183 dtb->demapPage(vaddr, asn);
184 }
185
186 void dumpFuncProfile();
187
188 Fault hwrei();
189
190 bool simPalCheck(int palFunc);
191
192 /*******************************************
193 * ThreadContext interface functions.
194 ******************************************/
195
196 BaseCPU *getCpuPtr() { return baseCpu; }
197
198 BaseTLB *getITBPtr() { return itb; }
199
200 BaseTLB *getDTBPtr() { return dtb; }
201
202 CheckerCPU *getCheckerCpuPtr() { return NULL; }
203
204 TheISA::Decoder *getDecoderPtr() { return &decoder; }
205
206 System *getSystemPtr() { return system; }
207
208 Status status() const { return _status; }
209
210 void setStatus(Status newStatus) { _status = newStatus; }
211
212 /// Set the status to Active.
213 void activate();
214
215 /// Set the status to Suspended.
216 void suspend();
217
218 /// Set the status to Halted.
219 void halt();
220
221 void copyArchRegs(ThreadContext *tc);
222
223 void clearArchRegs()
224 {
225 _pcState = 0;
226 memset(intRegs, 0, sizeof(intRegs));
227 memset(floatRegs, 0, sizeof(floatRegs));
228 for (int i = 0; i < TheISA::NumVecRegs; i++) {
229 vecRegs[i].zero();
230 }
231#ifdef ISA_HAS_CC_REGS
232 memset(ccRegs, 0, sizeof(ccRegs));
233#endif
234 isa->clear();
235 }
236
237 //
238 // New accessors for new decoder.
239 //
240 RegVal
241 readIntReg(int reg_idx)
242 {
243 int flatIndex = isa->flattenIntIndex(reg_idx);
244 assert(flatIndex < TheISA::NumIntRegs);
245 uint64_t regVal(readIntRegFlat(flatIndex));
246 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
247 reg_idx, flatIndex, regVal);
248 return regVal;
249 }
250
251 RegVal
252 readFloatRegBits(int reg_idx)
253 {
254 int flatIndex = isa->flattenFloatIndex(reg_idx);
255 assert(flatIndex < TheISA::NumFloatRegs);
256 RegVal regVal(readFloatRegBitsFlat(flatIndex));
257 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
258 reg_idx, flatIndex, regVal);
259 return regVal;
260 }
261
262 const VecRegContainer&
263 readVecReg(const RegId& reg) const
264 {
265 int flatIndex = isa->flattenVecIndex(reg.index());
266 assert(flatIndex < TheISA::NumVecRegs);
267 const VecRegContainer& regVal = readVecRegFlat(flatIndex);
268 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
269 reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print());
270 return regVal;
271 }
272
273 VecRegContainer&
274 getWritableVecReg(const RegId& reg)
275 {
276 int flatIndex = isa->flattenVecIndex(reg.index());
277 assert(flatIndex < TheISA::NumVecRegs);
278 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
279 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
280 reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print());
281 return regVal;
282 }
283
284 /** Vector Register Lane Interfaces. */
285 /** @{ */
286 /** Reads source vector <T> operand. */
287 template <typename T>
288 VecLaneT<T, true>
289 readVecLane(const RegId& reg) const
290 {
291 int flatIndex = isa->flattenVecIndex(reg.index());
292 assert(flatIndex < TheISA::NumVecRegs);
293 auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex());
294 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n",
295 reg.index(), flatIndex, reg.elemIndex(), regVal);
296 return regVal;
297 }
298
299 /** Reads source vector 8bit operand. */
300 virtual ConstVecLane8
301 readVec8BitLaneReg(const RegId& reg) const
302 { return readVecLane<uint8_t>(reg); }
303
304 /** Reads source vector 16bit operand. */
305 virtual ConstVecLane16
306 readVec16BitLaneReg(const RegId& reg) const
307 { return readVecLane<uint16_t>(reg); }
308
309 /** Reads source vector 32bit operand. */
310 virtual ConstVecLane32
311 readVec32BitLaneReg(const RegId& reg) const
312 { return readVecLane<uint32_t>(reg); }
313
314 /** Reads source vector 64bit operand. */
315 virtual ConstVecLane64
316 readVec64BitLaneReg(const RegId& reg) const
317 { return readVecLane<uint64_t>(reg); }
318
319 /** Write a lane of the destination vector register. */
320 template <typename LD>
321 void setVecLaneT(const RegId& reg, const LD& val)
322 {
323 int flatIndex = isa->flattenVecIndex(reg.index());
324 assert(flatIndex < TheISA::NumVecRegs);
325 setVecLaneFlat(flatIndex, reg.elemIndex(), val);
326 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n",
327 reg.index(), flatIndex, reg.elemIndex(), val);
328 }
329 virtual void setVecLane(const RegId& reg,
330 const LaneData<LaneSize::Byte>& val)
331 { return setVecLaneT(reg, val); }
332 virtual void setVecLane(const RegId& reg,
333 const LaneData<LaneSize::TwoByte>& val)
334 { return setVecLaneT(reg, val); }
335 virtual void setVecLane(const RegId& reg,
336 const LaneData<LaneSize::FourByte>& val)
337 { return setVecLaneT(reg, val); }
338 virtual void setVecLane(const RegId& reg,
339 const LaneData<LaneSize::EightByte>& val)
340 { return setVecLaneT(reg, val); }
341 /** @} */
342
343 const VecElem& readVecElem(const RegId& reg) const
344 {
345 int flatIndex = isa->flattenVecElemIndex(reg.index());
346 assert(flatIndex < TheISA::NumVecRegs);
347 const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex());
348 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
349 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
350 return regVal;
351 }
352
353
354 CCReg readCCReg(int reg_idx)
355 {
356#ifdef ISA_HAS_CC_REGS
357 int flatIndex = isa->flattenCCIndex(reg_idx);
358 assert(0 <= flatIndex);
359 assert(flatIndex < TheISA::NumCCRegs);
360 uint64_t regVal(readCCRegFlat(flatIndex));
361 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
362 reg_idx, flatIndex, regVal);
363 return regVal;
364#else
365 panic("Tried to read a CC register.");
366 return 0;
367#endif
368 }
369
370 void
371 setIntReg(int reg_idx, RegVal val)
372 {
373 int flatIndex = isa->flattenIntIndex(reg_idx);
374 assert(flatIndex < TheISA::NumIntRegs);
375 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
376 reg_idx, flatIndex, val);
377 setIntRegFlat(flatIndex, val);
378 }
379
380 void
381 setFloatRegBits(int reg_idx, RegVal val)
382 {
383 int flatIndex = isa->flattenFloatIndex(reg_idx);
384 assert(flatIndex < TheISA::NumFloatRegs);
385 // XXX: Fix array out of bounds compiler error for gem5.fast
386 // when checkercpu enabled
387 if (flatIndex < TheISA::NumFloatRegs)
388 setFloatRegBitsFlat(flatIndex, val);
389 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n",
390 reg_idx, flatIndex, val);
391 }
392
393 void
394 setVecReg(const RegId& reg, const VecRegContainer& val)
395 {
396 int flatIndex = isa->flattenVecIndex(reg.index());
397 assert(flatIndex < TheISA::NumVecRegs);
398 setVecRegFlat(flatIndex, val);
399 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n",
400 reg.index(), flatIndex, val.print());
401 }
402
403 void
404 setVecElem(const RegId& reg, const VecElem& val)
405 {
406 int flatIndex = isa->flattenVecElemIndex(reg.index());
407 assert(flatIndex < TheISA::NumVecRegs);
408 setVecElemFlat(flatIndex, reg.elemIndex(), val);
409 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to"
410 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
411 }
412
413 void
414 setCCReg(int reg_idx, CCReg val)
415 {
416#ifdef ISA_HAS_CC_REGS
417 int flatIndex = isa->flattenCCIndex(reg_idx);
418 assert(flatIndex < TheISA::NumCCRegs);
419 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
420 reg_idx, flatIndex, val);
421 setCCRegFlat(flatIndex, val);
422#else
423 panic("Tried to set a CC register.");
424#endif
425 }
426
427 TheISA::PCState
428 pcState()
429 {
430 return _pcState;
431 }
432
433 void
434 pcState(const TheISA::PCState &val)
435 {
436 _pcState = val;
437 }
438
439 void
440 pcStateNoRecord(const TheISA::PCState &val)
441 {
442 _pcState = val;
443 }
444
445 Addr
446 instAddr()
447 {
448 return _pcState.instAddr();
449 }
450
451 Addr
452 nextInstAddr()
453 {
454 return _pcState.nextInstAddr();
455 }
456
457 void
458 setNPC(Addr val)
459 {
460 _pcState.setNPC(val);
461 }
462
463 MicroPC
464 microPC()
465 {
466 return _pcState.microPC();
467 }
468
469 bool readPredicate()
470 {
471 return predicate;
472 }
473
474 void setPredicate(bool val)
475 {
476 predicate = val;
477 }
478
479 RegVal
480 readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
481 {
482 return isa->readMiscRegNoEffect(misc_reg);
483 }
484
485 RegVal
486 readMiscReg(int misc_reg, ThreadID tid=0)
487 {
488 return isa->readMiscReg(misc_reg, tc);
489 }
490
491 void
492 setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0)
493 {
494 return isa->setMiscRegNoEffect(misc_reg, val);
495 }
496
497 void
498 setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0)
499 {
500 return isa->setMiscReg(misc_reg, val, tc);
501 }
502
503 RegId
504 flattenRegId(const RegId& regId) const
505 {
506 return isa->flattenRegId(regId);
507 }
508
509 unsigned readStCondFailures() { return storeCondFailures; }
510
511 void setStCondFailures(unsigned sc_failures)
512 { storeCondFailures = sc_failures; }
513
514 void
515 syscall(int64_t callnum, Fault *fault)
516 {
517 process->syscall(callnum, tc, fault);
518 }
519
520 RegVal readIntRegFlat(int idx) { return intRegs[idx]; }
521 void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; }
522
523 RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; }
524 void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; }
525
526 const VecRegContainer &
527 readVecRegFlat(const RegIndex& reg) const
528 {
529 return vecRegs[reg];
530 }
531
532 VecRegContainer &
533 getWritableVecRegFlat(const RegIndex& reg)
534 {
535 return vecRegs[reg];
536 }
537
538 void
539 setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
540 {
541 vecRegs[reg] = val;
542 }
543
544 template <typename T>
545 VecLaneT
546 readVecLaneFlat(const RegIndex& reg, int lId) const
547 {
548 return vecRegs[reg].laneView<T>(lId);
549 }
550
551 template <typename LD>
552 void
553 setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
554 {
555 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
556 }
557
558 const VecElem &
559 readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const
560 {
561 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
562 }
563
564 void
565 setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
566 const VecElem val)
567 {
568 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
569 }
570
571#ifdef ISA_HAS_CC_REGS
572 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
573 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
574#else
575 CCReg readCCRegFlat(int idx)
576 { panic("readCCRegFlat w/no CC regs!\n"); }
577
578 void setCCRegFlat(int idx, CCReg val)
579 { panic("setCCRegFlat w/no CC regs!\n"); }
580#endif
581};
582
583
584#endif // __CPU_CPU_EXEC_CONTEXT_HH__