1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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123 /** The next pc.
124 */
125 Addr nextPC;
126
127 /** The next next pc.
128 */
129 Addr nextNPC;
130
131 /** Did this instruction execute or is it predicated false */
132 bool predicate;
133
134 public:
135 // pointer to CPU associated with this SimpleThread
136 BaseCPU *cpu;
137
138 ProxyThreadContext<SimpleThread> *tc;
139
140 System *system;
141

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369
370 void setNextNPC(uint64_t val)
371 {
372#if ISA_HAS_DELAY_SLOT
373 nextNPC = val;
374#endif
375 }
376
377 bool readPredicate()
378 {
379 return predicate;
380 }
381
382 void setPredicate(bool val)
383 {
384 predicate = val;
385 }
386
387 MiscReg
388 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
389 {
390 return isa.readMiscRegNoEffect(misc_reg);
391 }
392
393 MiscReg
394 readMiscReg(int misc_reg, ThreadID tid = 0)

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