1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa.hh"
36#include "arch/isa_traits.hh"
37#include "arch/regfile.hh"
38#include "arch/tlb.hh"
39#include "base/types.hh"
40#include "config/full_system.hh"
41#include "cpu/thread_context.hh"
42#include "cpu/thread_state.hh"
43#include "mem/request.hh"

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86 * examples.
87 */
88
89class SimpleThread : public ThreadState
90{
91 protected:
92 typedef TheISA::RegFile RegFile;
93 typedef TheISA::MachInst MachInst;
94 typedef TheISA::MiscReg MiscReg;
95 typedef TheISA::FloatReg FloatReg;
96 typedef TheISA::FloatRegBits FloatRegBits;
97 public:
98 typedef ThreadContext::Status Status;
99
100 protected:
101 RegFile regs; // correct-path register context
102 TheISA::ISA isa; // one "instance" of the current ISA.
103
104 public:
105 // pointer to CPU associated with this SimpleThread
106 BaseCPU *cpu;
107
108 ProxyThreadContext<SimpleThread> *tc;
109
110 System *system;

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160 }
161
162 void demapDataPage(Addr vaddr, uint64_t asn)
163 {
164 dtb->demapPage(vaddr, asn);
165 }
166
167#if FULL_SYSTEM
168 int getInstAsid() { return isa.instAsid(); }
169 int getDataAsid() { return isa.dataAsid(); }
170
171 void dumpFuncProfile();
172
173 Fault hwrei();
174
175 bool simPalCheck(int palFunc);
176
177#endif

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225
226 void clearArchRegs() { regs.clear(); }
227
228 //
229 // New accessors for new decoder.
230 //
231 uint64_t readIntReg(int reg_idx)
232 {
233 int flatIndex = isa.flattenIntIndex(reg_idx);
234 return regs.readIntReg(flatIndex);
235 }
236
237 FloatReg readFloatReg(int reg_idx, int width)
238 {
239 int flatIndex = isa.flattenFloatIndex(reg_idx);
240 return regs.readFloatReg(flatIndex, width);
241 }
242
243 FloatReg readFloatReg(int reg_idx)
244 {
245 int flatIndex = isa.flattenFloatIndex(reg_idx);
246 return regs.readFloatReg(flatIndex);
247 }
248
249 FloatRegBits readFloatRegBits(int reg_idx, int width)
250 {
251 int flatIndex = isa.flattenFloatIndex(reg_idx);
252 return regs.readFloatRegBits(flatIndex, width);
253 }
254
255 FloatRegBits readFloatRegBits(int reg_idx)
256 {
257 int flatIndex = isa.flattenFloatIndex(reg_idx);
258 return regs.readFloatRegBits(flatIndex);
259 }
260
261 void setIntReg(int reg_idx, uint64_t val)
262 {
263 int flatIndex = isa.flattenIntIndex(reg_idx);
264 regs.setIntReg(flatIndex, val);
265 }
266
267 void setFloatReg(int reg_idx, FloatReg val, int width)
268 {
269 int flatIndex = isa.flattenFloatIndex(reg_idx);
270 regs.setFloatReg(flatIndex, val, width);
271 }
272
273 void setFloatReg(int reg_idx, FloatReg val)
274 {
275 int flatIndex = isa.flattenFloatIndex(reg_idx);
276 regs.setFloatReg(flatIndex, val);
277 }
278
279 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
280 {
281 int flatIndex = isa.flattenFloatIndex(reg_idx);
282 regs.setFloatRegBits(flatIndex, val, width);
283 }
284
285 void setFloatRegBits(int reg_idx, FloatRegBits val)
286 {
287 int flatIndex = isa.flattenFloatIndex(reg_idx);
288 regs.setFloatRegBits(flatIndex, val);
289 }
290
291 uint64_t readPC()
292 {
293 return regs.readPC();
294 }
295

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336 void setNextNPC(uint64_t val)
337 {
338 regs.setNextNPC(val);
339 }
340
341 MiscReg
342 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
343 {
344 return isa.readMiscRegNoEffect(misc_reg);
345 }
346
347 MiscReg
348 readMiscReg(int misc_reg, ThreadID tid = 0)
349 {
350 return isa.readMiscReg(misc_reg, tc);
351 }
352
353 void
354 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
355 {
356 return isa.setMiscRegNoEffect(misc_reg, val);
357 }
358
359 void
360 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
361 {
362 return isa.setMiscReg(misc_reg, val, tc);
363 }
364
365 int
366 flattenIntIndex(int reg)
367 {
368 return isa.flattenIntIndex(reg);
369 }
370
371 int
372 flattenFloatIndex(int reg)
373 {
374 return isa.flattenFloatIndex(reg);
375 }
376
377 unsigned readStCondFailures() { return storeCondFailures; }
378
379 void setStCondFailures(unsigned sc_failures)
380 { storeCondFailures = sc_failures; }
381
382#if !FULL_SYSTEM
383 void syscall(int64_t callnum)
384 {

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