1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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53#include "arch/types.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/thread_context.hh"
57#include "cpu/thread_state.hh"
58#include "debug/CCRegs.hh"
59#include "debug/FloatRegs.hh"
60#include "debug/IntRegs.hh"
61#include "mem/page_table.hh"
62#include "mem/request.hh"
63#include "sim/byteswap.hh"
64#include "sim/eventq.hh"
65#include "sim/process.hh"
66#include "sim/serialize.hh"
67#include "sim/system.hh"
68

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97class SimpleThread : public ThreadState
98{
99 protected:
100 typedef TheISA::MachInst MachInst;
101 typedef TheISA::MiscReg MiscReg;
102 typedef TheISA::FloatReg FloatReg;
103 typedef TheISA::FloatRegBits FloatRegBits;
104 typedef TheISA::CCReg CCReg;
105 public:
106 typedef ThreadContext::Status Status;
107
108 protected:
109 union {
110 FloatReg f[TheISA::NumFloatRegs];
111 FloatRegBits i[TheISA::NumFloatRegs];
112 } floatRegs;
113 TheISA::IntReg intRegs[TheISA::NumIntRegs];
114#ifdef ISA_HAS_CC_REGS
115 TheISA::CCReg ccRegs[TheISA::NumCCRegs];
116#endif
117 TheISA::ISA *const isa; // one "instance" of the current ISA.
118
119 TheISA::PCState _pcState;
120
121 /** Did this instruction execute or is it predicated false */
122 bool predicate;
123
124 public:

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277 reg_idx, flatIndex, regVal);
278 return regVal;
279#else
280 panic("Tried to read a CC register.");
281 return 0;
282#endif
283 }
284
285 void setIntReg(int reg_idx, uint64_t val)
286 {
287 int flatIndex = isa->flattenIntIndex(reg_idx);
288 assert(flatIndex < TheISA::NumIntRegs);
289 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
290 reg_idx, flatIndex, val);
291 setIntRegFlat(flatIndex, val);
292 }

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320 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
321 reg_idx, flatIndex, val);
322 setCCRegFlat(flatIndex, val);
323#else
324 panic("Tried to set a CC register.");
325#endif
326 }
327
328 TheISA::PCState
329 pcState()
330 {
331 return _pcState;
332 }
333
334 void
335 pcState(const TheISA::PCState &val)

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409
410 int
411 flattenCCIndex(int reg)
412 {
413 return isa->flattenCCIndex(reg);
414 }
415
416 int
417 flattenMiscIndex(int reg)
418 {
419 return isa->flattenMiscIndex(reg);
420 }
421
422 unsigned readStCondFailures() { return storeCondFailures; }
423
424 void setStCondFailures(unsigned sc_failures)

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445 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
446#else
447 CCReg readCCRegFlat(int idx)
448 { panic("readCCRegFlat w/no CC regs!\n"); }
449
450 void setCCRegFlat(int idx, CCReg val)
451 { panic("setCCRegFlat w/no CC regs!\n"); }
452#endif
453};
454
455
456#endif // __CPU_CPU_EXEC_CONTEXT_HH__