simple_thread.cc (8767:e575781f71b8) simple_thread.cc (8777:dd43f1c9fa0a)
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/utility.hh"
38#include "config/the_isa.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/thread_context.hh"
42#include "mem/vport.hh"
43#include "params/BaseCPU.hh"
44#include "sim/process.hh"
45
46#if FULL_SYSTEM
47#include "arch/kernel_stats.hh"
48#include "arch/stacktrace.hh"
37#include "arch/kernel_stats.hh"
38#include "arch/stacktrace.hh"
39#include "arch/utility.hh"
49#include "base/callback.hh"
50#include "base/cprintf.hh"
51#include "base/output.hh"
52#include "base/trace.hh"
40#include "base/callback.hh"
41#include "base/cprintf.hh"
42#include "base/output.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/base.hh"
53#include "cpu/profile.hh"
54#include "cpu/quiesce_event.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/thread_context.hh"
50#include "mem/translating_port.hh"
51#include "mem/vport.hh"
52#include "params/BaseCPU.hh"
53#include "sim/process.hh"
55#include "sim/serialize.hh"
56#include "sim/sim_exit.hh"
54#include "sim/serialize.hh"
55#include "sim/sim_exit.hh"
57#else
58#include "mem/translating_port.hh"
59#include "sim/system.hh"
56#include "sim/system.hh"
60#endif
61
62using namespace std;
63
64// constructor
65#if !FULL_SYSTEM
66SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
67 TheISA::TLB *_itb, TheISA::TLB *_dtb)
68 : ThreadState(_cpu, _thread_num, _process),

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206 // thread_num and cpu_id are deterministic from the config
207
208 //
209 // Now must unserialize all the ISA dependent state
210 //
211 isa.unserialize(cpu, cp, section);
212}
213
57
58using namespace std;
59
60// constructor
61#if !FULL_SYSTEM
62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
63 TheISA::TLB *_itb, TheISA::TLB *_dtb)
64 : ThreadState(_cpu, _thread_num, _process),

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202 // thread_num and cpu_id are deterministic from the config
203
204 //
205 // Now must unserialize all the ISA dependent state
206 //
207 isa.unserialize(cpu, cp, section);
208}
209
214#if FULL_SYSTEM
215void
216SimpleThread::dumpFuncProfile()
217{
218 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
219 profile->dump(tc, *os);
220}
210void
211SimpleThread::dumpFuncProfile()
212{
213 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
214 profile->dump(tc, *os);
215}
221#endif
222
223void
224SimpleThread::activate(int delay)
225{
226 if (status() == ThreadContext::Active)
227 return;
228
229 lastActivate = curTick();

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217void
218SimpleThread::activate(int delay)
219{
220 if (status() == ThreadContext::Active)
221 return;
222
223 lastActivate = curTick();

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