simple_thread.cc (8761:20322354b80b) simple_thread.cc (8766:b0773af78423)
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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57#include "mem/translating_port.hh"
58#include "sim/process.hh"
59#include "sim/system.hh"
60#endif
61
62using namespace std;
63
64// constructor
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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57#include "mem/translating_port.hh"
58#include "sim/process.hh"
59#include "sim/system.hh"
60#endif
61
62using namespace std;
63
64// constructor
65#if FULL_SYSTEM
65#if !FULL_SYSTEM
66SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
67 TheISA::TLB *_itb, TheISA::TLB *_dtb)
68 : ThreadState(_cpu, _thread_num, _process),
69 cpu(_cpu), itb(_itb), dtb(_dtb)
70{
71 clearArchRegs();
72 tc = new ProxyThreadContext<SimpleThread>(this);
73}
74#else
66SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
67 TheISA::TLB *_itb, TheISA::TLB *_dtb,
68 bool use_kernel_stats)
75SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
76 TheISA::TLB *_itb, TheISA::TLB *_dtb,
77 bool use_kernel_stats)
69 : ThreadState(_cpu, _thread_num),
78 : ThreadState(_cpu, _thread_num, NULL),
70 cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb)
71
72{
73 tc = new ProxyThreadContext<SimpleThread>(this);
74
75 quiesceEvent = new EndQuiesceEvent(tc);
76
77 clearArchRegs();

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88 // on the first cycle when there's no node available.
89 static ProfileNode dummyNode;
90 profileNode = &dummyNode;
91 profilePC = 3;
92
93 if (use_kernel_stats)
94 kernelStats = new TheISA::Kernel::Statistics(system);
95}
79 cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb)
80
81{
82 tc = new ProxyThreadContext<SimpleThread>(this);
83
84 quiesceEvent = new EndQuiesceEvent(tc);
85
86 clearArchRegs();

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97 // on the first cycle when there's no node available.
98 static ProfileNode dummyNode;
99 profileNode = &dummyNode;
100 profilePC = 3;
101
102 if (use_kernel_stats)
103 kernelStats = new TheISA::Kernel::Statistics(system);
104}
96#else
97SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
98 TheISA::TLB *_itb, TheISA::TLB *_dtb)
99 : ThreadState(_cpu, _thread_num, _process),
100 cpu(_cpu), itb(_itb), dtb(_dtb)
101{
102 clearArchRegs();
103 tc = new ProxyThreadContext<SimpleThread>(this);
104}
105
106#endif
107
108SimpleThread::SimpleThread()
105#endif
106
107SimpleThread::SimpleThread()
109#if FULL_SYSTEM
110 : ThreadState(NULL, -1)
111#else
112 : ThreadState(NULL, -1, NULL)
108 : ThreadState(NULL, -1, NULL)
113#endif
114{
115 tc = new ProxyThreadContext<SimpleThread>(this);
116}
117
118SimpleThread::~SimpleThread()
119{
120 delete physPort;
121 delete virtPort;

--- 174 unchanged lines hidden --- 		109{
110 tc = new ProxyThreadContext<SimpleThread>(this);
111}
112
113SimpleThread::~SimpleThread()
114{
115 delete physPort;
116 delete virtPort;

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