1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
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38#include "config/the_isa.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/thread_context.hh"
42#include "params/BaseCPU.hh"
43
44#if FULL_SYSTEM
45#include "arch/kernel_stats.hh"
46#include "arch/stacktrace.hh"
47#include "base/callback.hh"
48#include "base/cprintf.hh"
49#include "base/output.hh"
50#include "base/trace.hh"
51#include "cpu/profile.hh"
52#include "cpu/quiesce_event.hh"
53#include "sim/serialize.hh"
54#include "sim/sim_exit.hh"
55#else
56#include "mem/translating_port.hh"
57#include "sim/process.hh"
58#include "sim/system.hh"
59#endif
60
61using namespace std;
62
63// constructor
64#if FULL_SYSTEM
65SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
66 TheISA::TLB *_itb, TheISA::TLB *_dtb,
67 bool use_kernel_stats)
68 : ThreadState(_cpu, _thread_num),
69 cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb)
70
71{
72 tc = new ProxyThreadContext<SimpleThread>(this);
73
74 quiesceEvent = new EndQuiesceEvent(tc);
75
76 clearArchRegs();
77
78 if (cpu->params()->profile) {
79 profile = new FunctionProfile(system->kernelSymtab);
80 Callback *cb =
81 new MakeCallback<SimpleThread,
82 &SimpleThread::dumpFuncProfile>(this);
83 registerExitCallback(cb);
84 }
85
86 // let's fill with a dummy node for now so we don't get a segfault
87 // on the first cycle when there's no node available.
88 static ProfileNode dummyNode;
89 profileNode = &dummyNode;
90 profilePC = 3;
91
92 if (use_kernel_stats)
93 kernelStats = new TheISA::Kernel::Statistics(system);
94}
95#else
96SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
97 TheISA::TLB *_itb, TheISA::TLB *_dtb)
98 : ThreadState(_cpu, _thread_num, _process),
99 cpu(_cpu), itb(_itb), dtb(_dtb)
100{
101 clearArchRegs();
102 tc = new ProxyThreadContext<SimpleThread>(this);
103}
104
105#endif
106
107SimpleThread::SimpleThread()
108#if FULL_SYSTEM
109 : ThreadState(NULL, -1)
110#else
111 : ThreadState(NULL, -1, NULL)
112#endif
113{
114 tc = new ProxyThreadContext<SimpleThread>(this);
115}
116
117SimpleThread::~SimpleThread()
118{
119#if FULL_SYSTEM
120 delete physPort;
121 delete virtPort;
122#endif
123 delete tc;
124}
125
126void
127SimpleThread::takeOverFrom(ThreadContext *oldContext)
128{
129 // some things should already be set up
130#if FULL_SYSTEM
131 assert(system == oldContext->getSystemPtr());
132#else
133 assert(process == oldContext->getProcessPtr());
134#endif
135
136 copyState(oldContext);
137#if FULL_SYSTEM
138 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
139 if (quiesce) {
140 // Point the quiesce event's TC at this TC so that it wakes up
141 // the proper CPU.
142 quiesce->tc = tc;
143 }
144 if (quiesceEvent) {
145 quiesceEvent->tc = tc;
146 }
147
148 TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
149 if (stats) {
150 kernelStats = stats;
151 }
152#endif
153
154 storeCondFailures = 0;
155
156 oldContext->setStatus(ThreadContext::Halted);
157}
158
159void
160SimpleThread::copyTC(ThreadContext *context)
161{
162 copyState(context);
163
164#if FULL_SYSTEM
165 EndQuiesceEvent *quiesce = context->getQuiesceEvent();
166 if (quiesce) {
167 quiesceEvent = quiesce;
168 }
169 TheISA::Kernel::Statistics *stats = context->getKernelStats();
170 if (stats) {
171 kernelStats = stats;
172 }
173#endif
174}
175
176void
177SimpleThread::copyState(ThreadContext *oldContext)
178{
179 // copy over functional state
180 _status = oldContext->status();
181 copyArchRegs(oldContext);
182#if !FULL_SYSTEM
183 funcExeInst = oldContext->readFuncExeInst();
184#endif
185
186 _threadId = oldContext->threadId();
187 _contextId = oldContext->contextId();
188}
189
190void
191SimpleThread::serialize(ostream &os)
192{
193 ThreadState::serialize(os);
194 SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
195 SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
196 SERIALIZE_SCALAR(microPC);
197 SERIALIZE_SCALAR(nextMicroPC);
198 SERIALIZE_SCALAR(PC);
199 SERIALIZE_SCALAR(nextPC);
200 SERIALIZE_SCALAR(nextNPC);
201 // thread_num and cpu_id are deterministic from the config
202
203 //
204 // Now must serialize all the ISA dependent state
205 //
206 isa.serialize(cpu, os);
207}
208
209
210void
211SimpleThread::unserialize(Checkpoint *cp, const std::string §ion)
212{
213 ThreadState::unserialize(cp, section);
214 UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
215 UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
216 UNSERIALIZE_SCALAR(microPC);
217 UNSERIALIZE_SCALAR(nextMicroPC);
218 UNSERIALIZE_SCALAR(PC);
219 UNSERIALIZE_SCALAR(nextPC);
220 UNSERIALIZE_SCALAR(nextNPC);
221 // thread_num and cpu_id are deterministic from the config
222
223 //
224 // Now must unserialize all the ISA dependent state
225 //
226 isa.unserialize(cpu, cp, section);
227}
228
229#if FULL_SYSTEM
230void
231SimpleThread::dumpFuncProfile()
232{
233 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
234 profile->dump(tc, *os);
235}
236#endif
237
238void
239SimpleThread::activate(int delay)
240{
241 if (status() == ThreadContext::Active)
242 return;
243
244 lastActivate = curTick;
245
246// if (status() == ThreadContext::Unallocated) {
247// cpu->activateWhenReady(_threadId);
248// return;
249// }
250
251 _status = ThreadContext::Active;
252
253 // status() == Suspended
254 cpu->activateContext(_threadId, delay);
255}
256
257void
258SimpleThread::suspend()
259{
260 if (status() == ThreadContext::Suspended)
261 return;
262
263 lastActivate = curTick;
264 lastSuspend = curTick;
265/*
266#if FULL_SYSTEM
267 // Don't change the status from active if there are pending interrupts
268 if (cpu->checkInterrupts()) {
269 assert(status() == ThreadContext::Active);
270 return;
271 }
272#endif
273*/
274 _status = ThreadContext::Suspended;
275 cpu->suspendContext(_threadId);
276}
277
278
279void
280SimpleThread::halt()
281{
282 if (status() == ThreadContext::Halted)
283 return;
284
285 _status = ThreadContext::Halted;
286 cpu->haltContext(_threadId);
287}
288
289
290void
291SimpleThread::regStats(const string &name)
292{
293#if FULL_SYSTEM
294 if (kernelStats)
295 kernelStats->regStats(name + ".kern");
296#endif
297}
298
299void
300SimpleThread::copyArchRegs(ThreadContext *src_tc)
301{
302 TheISA::copyRegs(src_tc, tc);
303}
304
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