1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 93 unchanged lines hidden (view full) --- 102 cpu->name(), tid)); 103 mem_port = system->physmem->getPort("functional"); 104 mem_port->setPeer(virtPort); 105 virtPort->setPeer(mem_port); 106} 107#else 108SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, 109 Process *_process, int _asid, MemObject* memobj) |
110 : ThreadState(-1, _thread_num, _process, _asid, memobj), |
111 cpu(_cpu) 112{ 113 /* Use this port to for syscall emulation writes to memory. */ 114 Port *mem_port; 115 port = new TranslatingPort(csprintf("%s-%d-funcport", 116 cpu->name(), tid), 117 process->pTable, false); 118 mem_port = memobj->getPort("functional"); 119 mem_port->setPeer(port); 120 port->setPeer(mem_port); 121 122 regs.clear(); 123 tc = new ProxyThreadContext<SimpleThread>(this); 124} 125 126SimpleThread::SimpleThread(RegFile *regFile) |
127 : ThreadState(-1, -1, NULL, -1, NULL), cpu(NULL) |
128{ 129 regs = *regFile; 130 tc = new ProxyThreadContext<SimpleThread>(this); 131} 132 133#endif 134 135SimpleThread::~SimpleThread() --- 190 unchanged lines hidden --- |