1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/kernel_stats.hh"
38#include "arch/stacktrace.hh"
39#include "arch/utility.hh"
40#include "base/callback.hh"
41#include "base/cprintf.hh"
42#include "base/output.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/base.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/thread_context.hh"
50#include "mem/fs_translating_port_proxy.hh"
51#include "mem/se_translating_port_proxy.hh"
52#include "params/BaseCPU.hh"
| 1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/kernel_stats.hh"
38#include "arch/stacktrace.hh"
39#include "arch/utility.hh"
40#include "base/callback.hh"
41#include "base/cprintf.hh"
42#include "base/output.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/base.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/thread_context.hh"
50#include "mem/fs_translating_port_proxy.hh"
51#include "mem/se_translating_port_proxy.hh"
52#include "params/BaseCPU.hh"
|
53#include "sim/full_system.hh"
54#include "sim/process.hh"
55#include "sim/serialize.hh"
56#include "sim/sim_exit.hh"
57#include "sim/system.hh"
58
59using namespace std;
60
61// constructor
62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
63 Process *_process, TheISA::TLB *_itb,
64 TheISA::TLB *_dtb, TheISA::ISA *_isa)
65 : ThreadState(_cpu, _thread_num, _process), isa(_isa), system(_sys),
66 itb(_itb), dtb(_dtb)
67{
68 clearArchRegs();
69 tc = new ProxyThreadContext<SimpleThread>(this);
70}
71
72SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
73 TheISA::TLB *_itb, TheISA::TLB *_dtb,
74 TheISA::ISA *_isa, bool use_kernel_stats)
75 : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
76 dtb(_dtb)
77{
78 tc = new ProxyThreadContext<SimpleThread>(this);
79
80 quiesceEvent = new EndQuiesceEvent(tc);
81
82 clearArchRegs();
83
84 if (baseCpu->params()->profile) {
85 profile = new FunctionProfile(system->kernelSymtab);
86 Callback *cb =
87 new MakeCallback<SimpleThread,
88 &SimpleThread::dumpFuncProfile>(this);
89 registerExitCallback(cb);
90 }
91
92 // let's fill with a dummy node for now so we don't get a segfault
93 // on the first cycle when there's no node available.
94 static ProfileNode dummyNode;
95 profileNode = &dummyNode;
96 profilePC = 3;
97
98 if (use_kernel_stats)
99 kernelStats = new TheISA::Kernel::Statistics(system);
100}
101
102SimpleThread::~SimpleThread()
103{
104 delete tc;
105}
106
107void
108SimpleThread::takeOverFrom(ThreadContext *oldContext)
109{
110 ::takeOverFrom(*tc, *oldContext);
111 decoder.takeOverFrom(oldContext->getDecoderPtr());
112
113 kernelStats = oldContext->getKernelStats();
114 funcExeInst = oldContext->readFuncExeInst();
115 storeCondFailures = 0;
116}
117
118void
119SimpleThread::copyState(ThreadContext *oldContext)
120{
121 // copy over functional state
122 _status = oldContext->status();
123 copyArchRegs(oldContext);
124 if (FullSystem)
125 funcExeInst = oldContext->readFuncExeInst();
126
127 _threadId = oldContext->threadId();
128 _contextId = oldContext->contextId();
129}
130
131void
132SimpleThread::serialize(ostream &os)
133{
134 ThreadState::serialize(os);
135 ::serialize(*tc, os);
136}
137
138
139void
140SimpleThread::unserialize(Checkpoint *cp, const std::string §ion)
141{
142 ThreadState::unserialize(cp, section);
143 ::unserialize(*tc, cp, section);
144}
145
146void
147SimpleThread::startup()
148{
149 isa->startup(tc);
150}
151
152void
153SimpleThread::dumpFuncProfile()
154{
155 std::ostream *os = simout.create(csprintf("profile.%s.dat",
156 baseCpu->name()));
157 profile->dump(tc, *os);
158}
159
160void
161SimpleThread::activate(Cycles delay)
162{
163 if (status() == ThreadContext::Active)
164 return;
165
166 lastActivate = curTick();
167
168// if (status() == ThreadContext::Unallocated) {
169// cpu->activateWhenReady(_threadId);
170// return;
171// }
172
173 _status = ThreadContext::Active;
174
175 // status() == Suspended
176 baseCpu->activateContext(_threadId, delay);
177}
178
179void
180SimpleThread::suspend()
181{
182 if (status() == ThreadContext::Suspended)
183 return;
184
185 lastActivate = curTick();
186 lastSuspend = curTick();
187 _status = ThreadContext::Suspended;
188 baseCpu->suspendContext(_threadId);
189}
190
191
192void
193SimpleThread::halt()
194{
195 if (status() == ThreadContext::Halted)
196 return;
197
198 _status = ThreadContext::Halted;
199 baseCpu->haltContext(_threadId);
200}
201
202
203void
204SimpleThread::regStats(const string &name)
205{
206 if (FullSystem && kernelStats)
207 kernelStats->regStats(name + ".kern");
208}
209
210void
211SimpleThread::copyArchRegs(ThreadContext *src_tc)
212{
213 TheISA::copyRegs(src_tc, tc);
214}
215
| 54#include "sim/full_system.hh"
55#include "sim/process.hh"
56#include "sim/serialize.hh"
57#include "sim/sim_exit.hh"
58#include "sim/system.hh"
59
60using namespace std;
61
62// constructor
63SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
64 Process *_process, TheISA::TLB *_itb,
65 TheISA::TLB *_dtb, TheISA::ISA *_isa)
66 : ThreadState(_cpu, _thread_num, _process), isa(_isa), system(_sys),
67 itb(_itb), dtb(_dtb)
68{
69 clearArchRegs();
70 tc = new ProxyThreadContext<SimpleThread>(this);
71}
72
73SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
74 TheISA::TLB *_itb, TheISA::TLB *_dtb,
75 TheISA::ISA *_isa, bool use_kernel_stats)
76 : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
77 dtb(_dtb)
78{
79 tc = new ProxyThreadContext<SimpleThread>(this);
80
81 quiesceEvent = new EndQuiesceEvent(tc);
82
83 clearArchRegs();
84
85 if (baseCpu->params()->profile) {
86 profile = new FunctionProfile(system->kernelSymtab);
87 Callback *cb =
88 new MakeCallback<SimpleThread,
89 &SimpleThread::dumpFuncProfile>(this);
90 registerExitCallback(cb);
91 }
92
93 // let's fill with a dummy node for now so we don't get a segfault
94 // on the first cycle when there's no node available.
95 static ProfileNode dummyNode;
96 profileNode = &dummyNode;
97 profilePC = 3;
98
99 if (use_kernel_stats)
100 kernelStats = new TheISA::Kernel::Statistics(system);
101}
102
103SimpleThread::~SimpleThread()
104{
105 delete tc;
106}
107
108void
109SimpleThread::takeOverFrom(ThreadContext *oldContext)
110{
111 ::takeOverFrom(*tc, *oldContext);
112 decoder.takeOverFrom(oldContext->getDecoderPtr());
113
114 kernelStats = oldContext->getKernelStats();
115 funcExeInst = oldContext->readFuncExeInst();
116 storeCondFailures = 0;
117}
118
119void
120SimpleThread::copyState(ThreadContext *oldContext)
121{
122 // copy over functional state
123 _status = oldContext->status();
124 copyArchRegs(oldContext);
125 if (FullSystem)
126 funcExeInst = oldContext->readFuncExeInst();
127
128 _threadId = oldContext->threadId();
129 _contextId = oldContext->contextId();
130}
131
132void
133SimpleThread::serialize(ostream &os)
134{
135 ThreadState::serialize(os);
136 ::serialize(*tc, os);
137}
138
139
140void
141SimpleThread::unserialize(Checkpoint *cp, const std::string §ion)
142{
143 ThreadState::unserialize(cp, section);
144 ::unserialize(*tc, cp, section);
145}
146
147void
148SimpleThread::startup()
149{
150 isa->startup(tc);
151}
152
153void
154SimpleThread::dumpFuncProfile()
155{
156 std::ostream *os = simout.create(csprintf("profile.%s.dat",
157 baseCpu->name()));
158 profile->dump(tc, *os);
159}
160
161void
162SimpleThread::activate(Cycles delay)
163{
164 if (status() == ThreadContext::Active)
165 return;
166
167 lastActivate = curTick();
168
169// if (status() == ThreadContext::Unallocated) {
170// cpu->activateWhenReady(_threadId);
171// return;
172// }
173
174 _status = ThreadContext::Active;
175
176 // status() == Suspended
177 baseCpu->activateContext(_threadId, delay);
178}
179
180void
181SimpleThread::suspend()
182{
183 if (status() == ThreadContext::Suspended)
184 return;
185
186 lastActivate = curTick();
187 lastSuspend = curTick();
188 _status = ThreadContext::Suspended;
189 baseCpu->suspendContext(_threadId);
190}
191
192
193void
194SimpleThread::halt()
195{
196 if (status() == ThreadContext::Halted)
197 return;
198
199 _status = ThreadContext::Halted;
200 baseCpu->haltContext(_threadId);
201}
202
203
204void
205SimpleThread::regStats(const string &name)
206{
207 if (FullSystem && kernelStats)
208 kernelStats->regStats(name + ".kern");
209}
210
211void
212SimpleThread::copyArchRegs(ThreadContext *src_tc)
213{
214 TheISA::copyRegs(src_tc, tc);
215}
216
|