1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "cpu/base.hh"
38#include "cpu/simple_thread.hh"
39#include "cpu/thread_context.hh"
40#include "params/BaseCPU.hh"
41
42#if FULL_SYSTEM
43#include "arch/kernel_stats.hh"
44#include "arch/stacktrace.hh"
45#include "base/callback.hh"
46#include "base/cprintf.hh"
47#include "base/output.hh"
48#include "base/trace.hh"
49#include "cpu/profile.hh"
50#include "cpu/quiesce_event.hh"
51#include "sim/serialize.hh"
52#include "sim/sim_exit.hh"
53#else
54#include "mem/translating_port.hh"
55#include "sim/process.hh"
56#include "sim/system.hh"
57#endif
58
59using namespace std;
60
61// constructor
62#if FULL_SYSTEM
63SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
64 TheISA::TLB *_itb, TheISA::TLB *_dtb,
65 bool use_kernel_stats)
66 : ThreadState(_cpu, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
67 dtb(_dtb)
68
69{
70 tc = new ProxyThreadContext<SimpleThread>(this);
71
72 quiesceEvent = new EndQuiesceEvent(tc);
73
74 regs.clear();
75
76 if (cpu->params()->profile) {
77 profile = new FunctionProfile(system->kernelSymtab);
78 Callback *cb =
79 new MakeCallback<SimpleThread,
80 &SimpleThread::dumpFuncProfile>(this);
81 registerExitCallback(cb);
82 }
83
84 // let's fill with a dummy node for now so we don't get a segfault
85 // on the first cycle when there's no node available.
86 static ProfileNode dummyNode;
87 profileNode = &dummyNode;
88 profilePC = 3;
89
90 if (use_kernel_stats)
91 kernelStats = new TheISA::Kernel::Statistics(system);
92}
93#else
94SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
95 TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid)
96 : ThreadState(_cpu, _thread_num, _process, _asid),
97 cpu(_cpu), itb(_itb), dtb(_dtb)
98{
99 regs.clear();
100 tc = new ProxyThreadContext<SimpleThread>(this);
101}
102
103#endif
104
105SimpleThread::SimpleThread()
106#if FULL_SYSTEM
107 : ThreadState(NULL, -1)
108#else
109 : ThreadState(NULL, -1, NULL, -1)
110#endif
111{
112 tc = new ProxyThreadContext<SimpleThread>(this);
113 regs.clear();
114}
115
116SimpleThread::~SimpleThread()
117{
118#if FULL_SYSTEM
119 delete physPort;
120 delete virtPort;
121#endif
122 delete tc;
123}
124
125void
126SimpleThread::takeOverFrom(ThreadContext *oldContext)
127{
128 // some things should already be set up
129#if FULL_SYSTEM
130 assert(system == oldContext->getSystemPtr());
131#else
132 assert(process == oldContext->getProcessPtr());
133#endif
134
135 copyState(oldContext);
136#if FULL_SYSTEM
137 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
138 if (quiesce) {
139 // Point the quiesce event's TC at this TC so that it wakes up
140 // the proper CPU.
141 quiesce->tc = tc;
142 }
143 if (quiesceEvent) {
144 quiesceEvent->tc = tc;
145 }
146
147 TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
148 if (stats) {
149 kernelStats = stats;
150 }
151#endif
152
153 storeCondFailures = 0;
154
155 oldContext->setStatus(ThreadContext::Halted);
156}
157
158void
159SimpleThread::copyTC(ThreadContext *context)
160{
161 copyState(context);
162
163#if FULL_SYSTEM
164 EndQuiesceEvent *quiesce = context->getQuiesceEvent();
165 if (quiesce) {
166 quiesceEvent = quiesce;
167 }
168 TheISA::Kernel::Statistics *stats = context->getKernelStats();
169 if (stats) {
170 kernelStats = stats;
171 }
172#endif
173}
174
175void
176SimpleThread::copyState(ThreadContext *oldContext)
177{
178 // copy over functional state
179 _status = oldContext->status();
180 copyArchRegs(oldContext);
181#if !FULL_SYSTEM
182 funcExeInst = oldContext->readFuncExeInst();
183#endif
184 inst = oldContext->getInst();
185
186 _threadId = oldContext->threadId();
187 _contextId = oldContext->contextId();
188}
189
190void
191SimpleThread::serialize(ostream &os)
192{
193 ThreadState::serialize(os);
194 regs.serialize(cpu, os);
| 1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "cpu/base.hh"
38#include "cpu/simple_thread.hh"
39#include "cpu/thread_context.hh"
40#include "params/BaseCPU.hh"
41
42#if FULL_SYSTEM
43#include "arch/kernel_stats.hh"
44#include "arch/stacktrace.hh"
45#include "base/callback.hh"
46#include "base/cprintf.hh"
47#include "base/output.hh"
48#include "base/trace.hh"
49#include "cpu/profile.hh"
50#include "cpu/quiesce_event.hh"
51#include "sim/serialize.hh"
52#include "sim/sim_exit.hh"
53#else
54#include "mem/translating_port.hh"
55#include "sim/process.hh"
56#include "sim/system.hh"
57#endif
58
59using namespace std;
60
61// constructor
62#if FULL_SYSTEM
63SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
64 TheISA::TLB *_itb, TheISA::TLB *_dtb,
65 bool use_kernel_stats)
66 : ThreadState(_cpu, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
67 dtb(_dtb)
68
69{
70 tc = new ProxyThreadContext<SimpleThread>(this);
71
72 quiesceEvent = new EndQuiesceEvent(tc);
73
74 regs.clear();
75
76 if (cpu->params()->profile) {
77 profile = new FunctionProfile(system->kernelSymtab);
78 Callback *cb =
79 new MakeCallback<SimpleThread,
80 &SimpleThread::dumpFuncProfile>(this);
81 registerExitCallback(cb);
82 }
83
84 // let's fill with a dummy node for now so we don't get a segfault
85 // on the first cycle when there's no node available.
86 static ProfileNode dummyNode;
87 profileNode = &dummyNode;
88 profilePC = 3;
89
90 if (use_kernel_stats)
91 kernelStats = new TheISA::Kernel::Statistics(system);
92}
93#else
94SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
95 TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid)
96 : ThreadState(_cpu, _thread_num, _process, _asid),
97 cpu(_cpu), itb(_itb), dtb(_dtb)
98{
99 regs.clear();
100 tc = new ProxyThreadContext<SimpleThread>(this);
101}
102
103#endif
104
105SimpleThread::SimpleThread()
106#if FULL_SYSTEM
107 : ThreadState(NULL, -1)
108#else
109 : ThreadState(NULL, -1, NULL, -1)
110#endif
111{
112 tc = new ProxyThreadContext<SimpleThread>(this);
113 regs.clear();
114}
115
116SimpleThread::~SimpleThread()
117{
118#if FULL_SYSTEM
119 delete physPort;
120 delete virtPort;
121#endif
122 delete tc;
123}
124
125void
126SimpleThread::takeOverFrom(ThreadContext *oldContext)
127{
128 // some things should already be set up
129#if FULL_SYSTEM
130 assert(system == oldContext->getSystemPtr());
131#else
132 assert(process == oldContext->getProcessPtr());
133#endif
134
135 copyState(oldContext);
136#if FULL_SYSTEM
137 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
138 if (quiesce) {
139 // Point the quiesce event's TC at this TC so that it wakes up
140 // the proper CPU.
141 quiesce->tc = tc;
142 }
143 if (quiesceEvent) {
144 quiesceEvent->tc = tc;
145 }
146
147 TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
148 if (stats) {
149 kernelStats = stats;
150 }
151#endif
152
153 storeCondFailures = 0;
154
155 oldContext->setStatus(ThreadContext::Halted);
156}
157
158void
159SimpleThread::copyTC(ThreadContext *context)
160{
161 copyState(context);
162
163#if FULL_SYSTEM
164 EndQuiesceEvent *quiesce = context->getQuiesceEvent();
165 if (quiesce) {
166 quiesceEvent = quiesce;
167 }
168 TheISA::Kernel::Statistics *stats = context->getKernelStats();
169 if (stats) {
170 kernelStats = stats;
171 }
172#endif
173}
174
175void
176SimpleThread::copyState(ThreadContext *oldContext)
177{
178 // copy over functional state
179 _status = oldContext->status();
180 copyArchRegs(oldContext);
181#if !FULL_SYSTEM
182 funcExeInst = oldContext->readFuncExeInst();
183#endif
184 inst = oldContext->getInst();
185
186 _threadId = oldContext->threadId();
187 _contextId = oldContext->contextId();
188}
189
190void
191SimpleThread::serialize(ostream &os)
192{
193 ThreadState::serialize(os);
194 regs.serialize(cpu, os);
|