1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 * Lisa Hsu 31 * Kevin Lim 32 */ 33 34#include <string> 35 36#include "arch/isa_traits.hh" 37#include "cpu/base.hh" 38#include "cpu/simple_thread.hh" 39#include "cpu/thread_context.hh"
| 1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 * Lisa Hsu 31 * Kevin Lim 32 */ 33 34#include <string> 35 36#include "arch/isa_traits.hh" 37#include "cpu/base.hh" 38#include "cpu/simple_thread.hh" 39#include "cpu/thread_context.hh"
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| 40#include "params/BaseCPU.hh"
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40 41#if FULL_SYSTEM 42#include "arch/kernel_stats.hh"
| 41 42#if FULL_SYSTEM 43#include "arch/kernel_stats.hh"
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| 44#include "arch/stacktrace.hh"
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43#include "base/callback.hh" 44#include "base/cprintf.hh" 45#include "base/output.hh" 46#include "base/trace.hh" 47#include "cpu/profile.hh" 48#include "cpu/quiesce_event.hh" 49#include "sim/serialize.hh" 50#include "sim/sim_exit.hh"
| 45#include "base/callback.hh" 46#include "base/cprintf.hh" 47#include "base/output.hh" 48#include "base/trace.hh" 49#include "cpu/profile.hh" 50#include "cpu/quiesce_event.hh" 51#include "sim/serialize.hh" 52#include "sim/sim_exit.hh"
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51#include "arch/stacktrace.hh"
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52#else
| 53#else
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| 54#include "mem/translating_port.hh"
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53#include "sim/process.hh" 54#include "sim/system.hh"
| 55#include "sim/process.hh" 56#include "sim/system.hh"
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55#include "mem/translating_port.hh"
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56#endif 57 58using namespace std; 59 60// constructor 61#if FULL_SYSTEM 62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 63 TheISA::ITB *_itb, TheISA::DTB *_dtb, 64 bool use_kernel_stats) 65 : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), 66 dtb(_dtb) 67 68{ 69 tc = new ProxyThreadContext<SimpleThread>(this); 70 71 quiesceEvent = new EndQuiesceEvent(tc); 72 73 regs.clear(); 74
| 57#endif 58 59using namespace std; 60 61// constructor 62#if FULL_SYSTEM 63SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 64 TheISA::ITB *_itb, TheISA::DTB *_dtb, 65 bool use_kernel_stats) 66 : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), 67 dtb(_dtb) 68 69{ 70 tc = new ProxyThreadContext<SimpleThread>(this); 71 72 quiesceEvent = new EndQuiesceEvent(tc); 73 74 regs.clear(); 75
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75 if (cpu->params->profile) {
| 76 if (cpu->params()->profile) {
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76 profile = new FunctionProfile(system->kernelSymtab); 77 Callback *cb = 78 new MakeCallback<SimpleThread, 79 &SimpleThread::dumpFuncProfile>(this); 80 registerExitCallback(cb); 81 } 82 83 // let's fill with a dummy node for now so we don't get a segfault 84 // on the first cycle when there's no node available. 85 static ProfileNode dummyNode; 86 profileNode = &dummyNode; 87 profilePC = 3; 88 89 if (use_kernel_stats) 90 kernelStats = new TheISA::Kernel::Statistics(system); 91} 92#else 93SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 94 TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid) 95 : ThreadState(_cpu, -1, _thread_num, _process, _asid), 96 cpu(_cpu), itb(_itb), dtb(_dtb) 97{ 98 regs.clear(); 99 tc = new ProxyThreadContext<SimpleThread>(this); 100} 101 102#endif 103 104SimpleThread::SimpleThread() 105#if FULL_SYSTEM 106 : ThreadState(NULL, -1, -1) 107#else 108 : ThreadState(NULL, -1, -1, NULL, -1) 109#endif 110{ 111 tc = new ProxyThreadContext<SimpleThread>(this); 112 regs.clear(); 113} 114 115SimpleThread::~SimpleThread() 116{ 117#if FULL_SYSTEM 118 delete physPort; 119 delete virtPort; 120#endif 121 delete tc; 122} 123 124void 125SimpleThread::takeOverFrom(ThreadContext *oldContext) 126{ 127 // some things should already be set up 128#if FULL_SYSTEM 129 assert(system == oldContext->getSystemPtr()); 130#else 131 assert(process == oldContext->getProcessPtr()); 132#endif 133 134 copyState(oldContext); 135#if FULL_SYSTEM 136 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 137 if (quiesce) { 138 // Point the quiesce event's TC at this TC so that it wakes up 139 // the proper CPU. 140 quiesce->tc = tc; 141 } 142 if (quiesceEvent) { 143 quiesceEvent->tc = tc; 144 } 145 146 TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 147 if (stats) { 148 kernelStats = stats; 149 } 150#endif 151 152 storeCondFailures = 0; 153 154 oldContext->setStatus(ThreadContext::Unallocated); 155} 156 157void 158SimpleThread::copyTC(ThreadContext *context) 159{ 160 copyState(context); 161 162#if FULL_SYSTEM 163 EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 164 if (quiesce) { 165 quiesceEvent = quiesce; 166 } 167 TheISA::Kernel::Statistics *stats = context->getKernelStats(); 168 if (stats) { 169 kernelStats = stats; 170 } 171#endif 172} 173 174void 175SimpleThread::copyState(ThreadContext *oldContext) 176{ 177 // copy over functional state 178 _status = oldContext->status(); 179 copyArchRegs(oldContext); 180 cpuId = oldContext->readCpuId(); 181#if !FULL_SYSTEM 182 funcExeInst = oldContext->readFuncExeInst(); 183#endif 184 inst = oldContext->getInst(); 185} 186 187void 188SimpleThread::serialize(ostream &os) 189{ 190 ThreadState::serialize(os); 191 regs.serialize(os); 192 // thread_num and cpu_id are deterministic from the config 193} 194 195 196void 197SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 198{ 199 ThreadState::unserialize(cp, section); 200 regs.unserialize(cp, section); 201 // thread_num and cpu_id are deterministic from the config 202} 203 204#if FULL_SYSTEM 205void 206SimpleThread::dumpFuncProfile() 207{ 208 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 209 profile->dump(tc, *os); 210} 211#endif 212 213void 214SimpleThread::activate(int delay) 215{ 216 if (status() == ThreadContext::Active) 217 return; 218 219 lastActivate = curTick; 220 221// if (status() == ThreadContext::Unallocated) { 222// cpu->activateWhenReady(tid); 223// return; 224// } 225 226 _status = ThreadContext::Active; 227 228 // status() == Suspended 229 cpu->activateContext(tid, delay); 230} 231 232void 233SimpleThread::suspend() 234{ 235 if (status() == ThreadContext::Suspended) 236 return; 237 238 lastActivate = curTick; 239 lastSuspend = curTick; 240/* 241#if FULL_SYSTEM 242 // Don't change the status from active if there are pending interrupts 243 if (cpu->check_interrupts()) { 244 assert(status() == ThreadContext::Active); 245 return; 246 } 247#endif 248*/ 249 _status = ThreadContext::Suspended; 250 cpu->suspendContext(tid); 251} 252 253void 254SimpleThread::deallocate() 255{ 256 if (status() == ThreadContext::Unallocated) 257 return; 258 259 _status = ThreadContext::Unallocated; 260 cpu->deallocateContext(tid); 261} 262 263void 264SimpleThread::halt() 265{ 266 if (status() == ThreadContext::Halted) 267 return; 268 269 _status = ThreadContext::Halted; 270 cpu->haltContext(tid); 271} 272 273 274void 275SimpleThread::regStats(const string &name) 276{ 277#if FULL_SYSTEM 278 if (kernelStats) 279 kernelStats->regStats(name + ".kern"); 280#endif 281} 282 283void 284SimpleThread::copyArchRegs(ThreadContext *src_tc) 285{ 286 TheISA::copyRegs(src_tc, tc); 287} 288
| 77 profile = new FunctionProfile(system->kernelSymtab); 78 Callback *cb = 79 new MakeCallback<SimpleThread, 80 &SimpleThread::dumpFuncProfile>(this); 81 registerExitCallback(cb); 82 } 83 84 // let's fill with a dummy node for now so we don't get a segfault 85 // on the first cycle when there's no node available. 86 static ProfileNode dummyNode; 87 profileNode = &dummyNode; 88 profilePC = 3; 89 90 if (use_kernel_stats) 91 kernelStats = new TheISA::Kernel::Statistics(system); 92} 93#else 94SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 95 TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid) 96 : ThreadState(_cpu, -1, _thread_num, _process, _asid), 97 cpu(_cpu), itb(_itb), dtb(_dtb) 98{ 99 regs.clear(); 100 tc = new ProxyThreadContext<SimpleThread>(this); 101} 102 103#endif 104 105SimpleThread::SimpleThread() 106#if FULL_SYSTEM 107 : ThreadState(NULL, -1, -1) 108#else 109 : ThreadState(NULL, -1, -1, NULL, -1) 110#endif 111{ 112 tc = new ProxyThreadContext<SimpleThread>(this); 113 regs.clear(); 114} 115 116SimpleThread::~SimpleThread() 117{ 118#if FULL_SYSTEM 119 delete physPort; 120 delete virtPort; 121#endif 122 delete tc; 123} 124 125void 126SimpleThread::takeOverFrom(ThreadContext *oldContext) 127{ 128 // some things should already be set up 129#if FULL_SYSTEM 130 assert(system == oldContext->getSystemPtr()); 131#else 132 assert(process == oldContext->getProcessPtr()); 133#endif 134 135 copyState(oldContext); 136#if FULL_SYSTEM 137 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 138 if (quiesce) { 139 // Point the quiesce event's TC at this TC so that it wakes up 140 // the proper CPU. 141 quiesce->tc = tc; 142 } 143 if (quiesceEvent) { 144 quiesceEvent->tc = tc; 145 } 146 147 TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 148 if (stats) { 149 kernelStats = stats; 150 } 151#endif 152 153 storeCondFailures = 0; 154 155 oldContext->setStatus(ThreadContext::Unallocated); 156} 157 158void 159SimpleThread::copyTC(ThreadContext *context) 160{ 161 copyState(context); 162 163#if FULL_SYSTEM 164 EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 165 if (quiesce) { 166 quiesceEvent = quiesce; 167 } 168 TheISA::Kernel::Statistics *stats = context->getKernelStats(); 169 if (stats) { 170 kernelStats = stats; 171 } 172#endif 173} 174 175void 176SimpleThread::copyState(ThreadContext *oldContext) 177{ 178 // copy over functional state 179 _status = oldContext->status(); 180 copyArchRegs(oldContext); 181 cpuId = oldContext->readCpuId(); 182#if !FULL_SYSTEM 183 funcExeInst = oldContext->readFuncExeInst(); 184#endif 185 inst = oldContext->getInst(); 186} 187 188void 189SimpleThread::serialize(ostream &os) 190{ 191 ThreadState::serialize(os); 192 regs.serialize(os); 193 // thread_num and cpu_id are deterministic from the config 194} 195 196 197void 198SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 199{ 200 ThreadState::unserialize(cp, section); 201 regs.unserialize(cp, section); 202 // thread_num and cpu_id are deterministic from the config 203} 204 205#if FULL_SYSTEM 206void 207SimpleThread::dumpFuncProfile() 208{ 209 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 210 profile->dump(tc, *os); 211} 212#endif 213 214void 215SimpleThread::activate(int delay) 216{ 217 if (status() == ThreadContext::Active) 218 return; 219 220 lastActivate = curTick; 221 222// if (status() == ThreadContext::Unallocated) { 223// cpu->activateWhenReady(tid); 224// return; 225// } 226 227 _status = ThreadContext::Active; 228 229 // status() == Suspended 230 cpu->activateContext(tid, delay); 231} 232 233void 234SimpleThread::suspend() 235{ 236 if (status() == ThreadContext::Suspended) 237 return; 238 239 lastActivate = curTick; 240 lastSuspend = curTick; 241/* 242#if FULL_SYSTEM 243 // Don't change the status from active if there are pending interrupts 244 if (cpu->check_interrupts()) { 245 assert(status() == ThreadContext::Active); 246 return; 247 } 248#endif 249*/ 250 _status = ThreadContext::Suspended; 251 cpu->suspendContext(tid); 252} 253 254void 255SimpleThread::deallocate() 256{ 257 if (status() == ThreadContext::Unallocated) 258 return; 259 260 _status = ThreadContext::Unallocated; 261 cpu->deallocateContext(tid); 262} 263 264void 265SimpleThread::halt() 266{ 267 if (status() == ThreadContext::Halted) 268 return; 269 270 _status = ThreadContext::Halted; 271 cpu->haltContext(tid); 272} 273 274 275void 276SimpleThread::regStats(const string &name) 277{ 278#if FULL_SYSTEM 279 if (kernelStats) 280 kernelStats->regStats(name + ".kern"); 281#endif 282} 283 284void 285SimpleThread::copyArchRegs(ThreadContext *src_tc) 286{ 287 TheISA::copyRegs(src_tc, tc); 288} 289
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