1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "cpu/base.hh"
38#include "cpu/simple_thread.hh"
39#include "cpu/thread_context.hh"
40
41#if FULL_SYSTEM
42#include "base/callback.hh"
43#include "base/cprintf.hh"
44#include "base/output.hh"
45#include "base/trace.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "kern/kernel_stats.hh"
49#include "sim/serialize.hh"
50#include "sim/sim_exit.hh"
51#include "arch/stacktrace.hh"
52#else
53#include "sim/process.hh"
54#include "sim/system.hh"
55#include "mem/translating_port.hh"
56#endif
57
58using namespace std;
59
60// constructor
61#if FULL_SYSTEM
62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
63 AlphaITB *_itb, AlphaDTB *_dtb,
64 bool use_kernel_stats)
65 : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
66 dtb(_dtb)
67
68{
69 tc = new ProxyThreadContext<SimpleThread>(this);
70
71 quiesceEvent = new EndQuiesceEvent(tc);
72
73 regs.clear();
74
75 if (cpu->params->profile) {
76 profile = new FunctionProfile(system->kernelSymtab);
77 Callback *cb =
78 new MakeCallback<SimpleThread,
79 &SimpleThread::dumpFuncProfile>(this);
80 registerExitCallback(cb);
81 }
82
83 // let's fill with a dummy node for now so we don't get a segfault
84 // on the first cycle when there's no node available.
85 static ProfileNode dummyNode;
86 profileNode = &dummyNode;
87 profilePC = 3;
88
89 if (use_kernel_stats) {
90 kernelStats = new Kernel::Statistics(system);
91 } else {
92 kernelStats = NULL;
93 }
94 Port *mem_port;
95 physPort = new FunctionalPort(csprintf("%s-%d-funcport",
96 cpu->name(), tid));
97 mem_port = system->physmem->getPort("functional");
98 mem_port->setPeer(physPort);
99 physPort->setPeer(mem_port);
100
101 virtPort = new VirtualPort(csprintf("%s-%d-vport",
102 cpu->name(), tid));
103 mem_port = system->physmem->getPort("functional");
104 mem_port->setPeer(virtPort);
105 virtPort->setPeer(mem_port);
106}
107#else
108SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
109 Process *_process, int _asid)
110 : ThreadState(_cpu, -1, _thread_num, _process, _asid),
111 cpu(_cpu)
112{
113 regs.clear();
114 tc = new ProxyThreadContext<SimpleThread>(this);
115}
116
117#endif
118
119SimpleThread::SimpleThread()
120#if FULL_SYSTEM
121 : ThreadState(NULL, -1, -1)
122#else
123 : ThreadState(NULL, -1, -1, NULL, -1)
124#endif
125{
126 tc = new ProxyThreadContext<SimpleThread>(this);
127 regs.clear();
128}
129
130SimpleThread::~SimpleThread()
131{
| 1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "cpu/base.hh"
38#include "cpu/simple_thread.hh"
39#include "cpu/thread_context.hh"
40
41#if FULL_SYSTEM
42#include "base/callback.hh"
43#include "base/cprintf.hh"
44#include "base/output.hh"
45#include "base/trace.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "kern/kernel_stats.hh"
49#include "sim/serialize.hh"
50#include "sim/sim_exit.hh"
51#include "arch/stacktrace.hh"
52#else
53#include "sim/process.hh"
54#include "sim/system.hh"
55#include "mem/translating_port.hh"
56#endif
57
58using namespace std;
59
60// constructor
61#if FULL_SYSTEM
62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
63 AlphaITB *_itb, AlphaDTB *_dtb,
64 bool use_kernel_stats)
65 : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
66 dtb(_dtb)
67
68{
69 tc = new ProxyThreadContext<SimpleThread>(this);
70
71 quiesceEvent = new EndQuiesceEvent(tc);
72
73 regs.clear();
74
75 if (cpu->params->profile) {
76 profile = new FunctionProfile(system->kernelSymtab);
77 Callback *cb =
78 new MakeCallback<SimpleThread,
79 &SimpleThread::dumpFuncProfile>(this);
80 registerExitCallback(cb);
81 }
82
83 // let's fill with a dummy node for now so we don't get a segfault
84 // on the first cycle when there's no node available.
85 static ProfileNode dummyNode;
86 profileNode = &dummyNode;
87 profilePC = 3;
88
89 if (use_kernel_stats) {
90 kernelStats = new Kernel::Statistics(system);
91 } else {
92 kernelStats = NULL;
93 }
94 Port *mem_port;
95 physPort = new FunctionalPort(csprintf("%s-%d-funcport",
96 cpu->name(), tid));
97 mem_port = system->physmem->getPort("functional");
98 mem_port->setPeer(physPort);
99 physPort->setPeer(mem_port);
100
101 virtPort = new VirtualPort(csprintf("%s-%d-vport",
102 cpu->name(), tid));
103 mem_port = system->physmem->getPort("functional");
104 mem_port->setPeer(virtPort);
105 virtPort->setPeer(mem_port);
106}
107#else
108SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
109 Process *_process, int _asid)
110 : ThreadState(_cpu, -1, _thread_num, _process, _asid),
111 cpu(_cpu)
112{
113 regs.clear();
114 tc = new ProxyThreadContext<SimpleThread>(this);
115}
116
117#endif
118
119SimpleThread::SimpleThread()
120#if FULL_SYSTEM
121 : ThreadState(NULL, -1, -1)
122#else
123 : ThreadState(NULL, -1, -1, NULL, -1)
124#endif
125{
126 tc = new ProxyThreadContext<SimpleThread>(this);
127 regs.clear();
128}
129
130SimpleThread::~SimpleThread()
131{
|
132 delete tc;
133}
134
135void
136SimpleThread::takeOverFrom(ThreadContext *oldContext)
137{
138 // some things should already be set up
139#if FULL_SYSTEM
140 assert(system == oldContext->getSystemPtr());
141#else
142 assert(process == oldContext->getProcessPtr());
143#endif
144
145 copyState(oldContext);
146#if FULL_SYSTEM
147 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
148 if (quiesce) {
149 // Point the quiesce event's TC at this TC so that it wakes up
150 // the proper CPU.
151 quiesce->tc = tc;
152 }
153 if (quiesceEvent) {
154 quiesceEvent->tc = tc;
155 }
156
157 Kernel::Statistics *stats = oldContext->getKernelStats();
158 if (stats) {
159 kernelStats = stats;
160 }
161#endif
162
163 storeCondFailures = 0;
164
165 oldContext->setStatus(ThreadContext::Unallocated);
166}
167
168void
169SimpleThread::copyTC(ThreadContext *context)
170{
171 copyState(context);
172
173#if FULL_SYSTEM
174 EndQuiesceEvent *quiesce = context->getQuiesceEvent();
175 if (quiesce) {
176 quiesceEvent = quiesce;
177 }
178 Kernel::Statistics *stats = context->getKernelStats();
179 if (stats) {
180 kernelStats = stats;
181 }
182#endif
183}
184
185void
186SimpleThread::copyState(ThreadContext *oldContext)
187{
188 // copy over functional state
189 _status = oldContext->status();
190 copyArchRegs(oldContext);
191 cpuId = oldContext->readCpuId();
192#if !FULL_SYSTEM
193 funcExeInst = oldContext->readFuncExeInst();
194#endif
195 inst = oldContext->getInst();
196}
197
198void
199SimpleThread::serialize(ostream &os)
200{
201 ThreadState::serialize(os);
202 regs.serialize(os);
203 // thread_num and cpu_id are deterministic from the config
204}
205
206
207void
208SimpleThread::unserialize(Checkpoint *cp, const std::string §ion)
209{
210 ThreadState::unserialize(cp, section);
211 regs.unserialize(cp, section);
212 // thread_num and cpu_id are deterministic from the config
213}
214
215#if FULL_SYSTEM
216void
217SimpleThread::dumpFuncProfile()
218{
219 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
220 profile->dump(tc, *os);
221}
222#endif
223
224void
225SimpleThread::activate(int delay)
226{
227 if (status() == ThreadContext::Active)
228 return;
229
230 lastActivate = curTick;
231
232 if (status() == ThreadContext::Unallocated) {
233 cpu->activateWhenReady(tid);
234 return;
235 }
236
237 _status = ThreadContext::Active;
238
239 // status() == Suspended
240 cpu->activateContext(tid, delay);
241}
242
243void
244SimpleThread::suspend()
245{
246 if (status() == ThreadContext::Suspended)
247 return;
248
249 lastActivate = curTick;
250 lastSuspend = curTick;
251/*
252#if FULL_SYSTEM
253 // Don't change the status from active if there are pending interrupts
254 if (cpu->check_interrupts()) {
255 assert(status() == ThreadContext::Active);
256 return;
257 }
258#endif
259*/
260 _status = ThreadContext::Suspended;
261 cpu->suspendContext(tid);
262}
263
264void
265SimpleThread::deallocate()
266{
267 if (status() == ThreadContext::Unallocated)
268 return;
269
270 _status = ThreadContext::Unallocated;
271 cpu->deallocateContext(tid);
272}
273
274void
275SimpleThread::halt()
276{
277 if (status() == ThreadContext::Halted)
278 return;
279
280 _status = ThreadContext::Halted;
281 cpu->haltContext(tid);
282}
283
284
285void
286SimpleThread::regStats(const string &name)
287{
288#if FULL_SYSTEM
289 if (kernelStats)
290 kernelStats->regStats(name + ".kern");
291#endif
292}
293
294void
295SimpleThread::copyArchRegs(ThreadContext *src_tc)
296{
297 TheISA::copyRegs(src_tc, tc);
298}
299
300#if FULL_SYSTEM
301VirtualPort*
302SimpleThread::getVirtPort(ThreadContext *src_tc)
303{
304 if (!src_tc)
305 return virtPort;
306
| 136 delete tc;
137}
138
139void
140SimpleThread::takeOverFrom(ThreadContext *oldContext)
141{
142 // some things should already be set up
143#if FULL_SYSTEM
144 assert(system == oldContext->getSystemPtr());
145#else
146 assert(process == oldContext->getProcessPtr());
147#endif
148
149 copyState(oldContext);
150#if FULL_SYSTEM
151 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
152 if (quiesce) {
153 // Point the quiesce event's TC at this TC so that it wakes up
154 // the proper CPU.
155 quiesce->tc = tc;
156 }
157 if (quiesceEvent) {
158 quiesceEvent->tc = tc;
159 }
160
161 Kernel::Statistics *stats = oldContext->getKernelStats();
162 if (stats) {
163 kernelStats = stats;
164 }
165#endif
166
167 storeCondFailures = 0;
168
169 oldContext->setStatus(ThreadContext::Unallocated);
170}
171
172void
173SimpleThread::copyTC(ThreadContext *context)
174{
175 copyState(context);
176
177#if FULL_SYSTEM
178 EndQuiesceEvent *quiesce = context->getQuiesceEvent();
179 if (quiesce) {
180 quiesceEvent = quiesce;
181 }
182 Kernel::Statistics *stats = context->getKernelStats();
183 if (stats) {
184 kernelStats = stats;
185 }
186#endif
187}
188
189void
190SimpleThread::copyState(ThreadContext *oldContext)
191{
192 // copy over functional state
193 _status = oldContext->status();
194 copyArchRegs(oldContext);
195 cpuId = oldContext->readCpuId();
196#if !FULL_SYSTEM
197 funcExeInst = oldContext->readFuncExeInst();
198#endif
199 inst = oldContext->getInst();
200}
201
202void
203SimpleThread::serialize(ostream &os)
204{
205 ThreadState::serialize(os);
206 regs.serialize(os);
207 // thread_num and cpu_id are deterministic from the config
208}
209
210
211void
212SimpleThread::unserialize(Checkpoint *cp, const std::string §ion)
213{
214 ThreadState::unserialize(cp, section);
215 regs.unserialize(cp, section);
216 // thread_num and cpu_id are deterministic from the config
217}
218
219#if FULL_SYSTEM
220void
221SimpleThread::dumpFuncProfile()
222{
223 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
224 profile->dump(tc, *os);
225}
226#endif
227
228void
229SimpleThread::activate(int delay)
230{
231 if (status() == ThreadContext::Active)
232 return;
233
234 lastActivate = curTick;
235
236 if (status() == ThreadContext::Unallocated) {
237 cpu->activateWhenReady(tid);
238 return;
239 }
240
241 _status = ThreadContext::Active;
242
243 // status() == Suspended
244 cpu->activateContext(tid, delay);
245}
246
247void
248SimpleThread::suspend()
249{
250 if (status() == ThreadContext::Suspended)
251 return;
252
253 lastActivate = curTick;
254 lastSuspend = curTick;
255/*
256#if FULL_SYSTEM
257 // Don't change the status from active if there are pending interrupts
258 if (cpu->check_interrupts()) {
259 assert(status() == ThreadContext::Active);
260 return;
261 }
262#endif
263*/
264 _status = ThreadContext::Suspended;
265 cpu->suspendContext(tid);
266}
267
268void
269SimpleThread::deallocate()
270{
271 if (status() == ThreadContext::Unallocated)
272 return;
273
274 _status = ThreadContext::Unallocated;
275 cpu->deallocateContext(tid);
276}
277
278void
279SimpleThread::halt()
280{
281 if (status() == ThreadContext::Halted)
282 return;
283
284 _status = ThreadContext::Halted;
285 cpu->haltContext(tid);
286}
287
288
289void
290SimpleThread::regStats(const string &name)
291{
292#if FULL_SYSTEM
293 if (kernelStats)
294 kernelStats->regStats(name + ".kern");
295#endif
296}
297
298void
299SimpleThread::copyArchRegs(ThreadContext *src_tc)
300{
301 TheISA::copyRegs(src_tc, tc);
302}
303
304#if FULL_SYSTEM
305VirtualPort*
306SimpleThread::getVirtPort(ThreadContext *src_tc)
307{
308 if (!src_tc)
309 return virtPort;
310
|