1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 * Lisa Hsu 31 * Kevin Lim 32 */ 33 34#include <string> 35 36#include "arch/isa_traits.hh" 37#include "cpu/base.hh" 38#include "cpu/simple_thread.hh" 39#include "cpu/thread_context.hh" 40 41#if FULL_SYSTEM 42#include "base/callback.hh" 43#include "base/cprintf.hh" 44#include "base/output.hh" 45#include "base/trace.hh" 46#include "cpu/profile.hh" 47#include "cpu/quiesce_event.hh" 48#include "kern/kernel_stats.hh" 49#include "sim/serialize.hh" 50#include "sim/sim_exit.hh" 51#include "arch/stacktrace.hh" 52#else 53#include "sim/process.hh" 54#include "sim/system.hh" 55#include "mem/translating_port.hh" 56#endif 57 58using namespace std; 59 60// constructor 61#if FULL_SYSTEM 62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
| 1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 * Lisa Hsu 31 * Kevin Lim 32 */ 33 34#include <string> 35 36#include "arch/isa_traits.hh" 37#include "cpu/base.hh" 38#include "cpu/simple_thread.hh" 39#include "cpu/thread_context.hh" 40 41#if FULL_SYSTEM 42#include "base/callback.hh" 43#include "base/cprintf.hh" 44#include "base/output.hh" 45#include "base/trace.hh" 46#include "cpu/profile.hh" 47#include "cpu/quiesce_event.hh" 48#include "kern/kernel_stats.hh" 49#include "sim/serialize.hh" 50#include "sim/sim_exit.hh" 51#include "arch/stacktrace.hh" 52#else 53#include "sim/process.hh" 54#include "sim/system.hh" 55#include "mem/translating_port.hh" 56#endif 57 58using namespace std; 59 60// constructor 61#if FULL_SYSTEM 62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
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63 AlphaITB *_itb, AlphaDTB *_dtb,
| 63 TheISA::ITB *_itb, TheISA::DTB *_dtb,
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64 bool use_kernel_stats)
| 64 bool use_kernel_stats)
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65 : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
| 65 : ThreadState(-1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
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66 dtb(_dtb) 67 68{ 69 tc = new ProxyThreadContext<SimpleThread>(this); 70 71 quiesceEvent = new EndQuiesceEvent(tc); 72 73 regs.clear(); 74 75 if (cpu->params->profile) { 76 profile = new FunctionProfile(system->kernelSymtab); 77 Callback *cb = 78 new MakeCallback<SimpleThread, 79 &SimpleThread::dumpFuncProfile>(this); 80 registerExitCallback(cb); 81 } 82 83 // let's fill with a dummy node for now so we don't get a segfault 84 // on the first cycle when there's no node available. 85 static ProfileNode dummyNode; 86 profileNode = &dummyNode; 87 profilePC = 3; 88 89 if (use_kernel_stats) { 90 kernelStats = new Kernel::Statistics(system); 91 } else { 92 kernelStats = NULL; 93 } 94 Port *mem_port; 95 physPort = new FunctionalPort(csprintf("%s-%d-funcport", 96 cpu->name(), tid)); 97 mem_port = system->physmem->getPort("functional"); 98 mem_port->setPeer(physPort); 99 physPort->setPeer(mem_port); 100 101 virtPort = new VirtualPort(csprintf("%s-%d-vport", 102 cpu->name(), tid)); 103 mem_port = system->physmem->getPort("functional"); 104 mem_port->setPeer(virtPort); 105 virtPort->setPeer(mem_port); 106} 107#else 108SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
| 66 dtb(_dtb) 67 68{ 69 tc = new ProxyThreadContext<SimpleThread>(this); 70 71 quiesceEvent = new EndQuiesceEvent(tc); 72 73 regs.clear(); 74 75 if (cpu->params->profile) { 76 profile = new FunctionProfile(system->kernelSymtab); 77 Callback *cb = 78 new MakeCallback<SimpleThread, 79 &SimpleThread::dumpFuncProfile>(this); 80 registerExitCallback(cb); 81 } 82 83 // let's fill with a dummy node for now so we don't get a segfault 84 // on the first cycle when there's no node available. 85 static ProfileNode dummyNode; 86 profileNode = &dummyNode; 87 profilePC = 3; 88 89 if (use_kernel_stats) { 90 kernelStats = new Kernel::Statistics(system); 91 } else { 92 kernelStats = NULL; 93 } 94 Port *mem_port; 95 physPort = new FunctionalPort(csprintf("%s-%d-funcport", 96 cpu->name(), tid)); 97 mem_port = system->physmem->getPort("functional"); 98 mem_port->setPeer(physPort); 99 physPort->setPeer(mem_port); 100 101 virtPort = new VirtualPort(csprintf("%s-%d-vport", 102 cpu->name(), tid)); 103 mem_port = system->physmem->getPort("functional"); 104 mem_port->setPeer(virtPort); 105 virtPort->setPeer(mem_port); 106} 107#else 108SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
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109 Process *_process, int _asid) 110 : ThreadState(_cpu, -1, _thread_num, _process, _asid),
| 109 Process *_process, int _asid, MemObject* memobj) 110 : ThreadState(-1, _thread_num, _process, _asid, memobj),
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111 cpu(_cpu) 112{
| 111 cpu(_cpu) 112{
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| 113 /* Use this port to for syscall emulation writes to memory. */ 114 Port *mem_port; 115 port = new TranslatingPort(csprintf("%s-%d-funcport", 116 cpu->name(), tid), 117 process->pTable, false); 118 mem_port = memobj->getPort("functional"); 119 mem_port->setPeer(port); 120 port->setPeer(mem_port); 121
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113 regs.clear(); 114 tc = new ProxyThreadContext<SimpleThread>(this); 115} 116 117#endif 118 119SimpleThread::SimpleThread() 120#if FULL_SYSTEM
| 122 regs.clear(); 123 tc = new ProxyThreadContext<SimpleThread>(this); 124} 125 126#endif 127 128SimpleThread::SimpleThread() 129#if FULL_SYSTEM
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121 : ThreadState(NULL, -1, -1)
| 130 : ThreadState(-1, -1)
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122#else
| 131#else
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123 : ThreadState(NULL, -1, -1, NULL, -1)
| 132 : ThreadState(-1, -1, NULL, -1, NULL)
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124#endif 125{ 126 tc = new ProxyThreadContext<SimpleThread>(this); 127 regs.clear(); 128} 129 130SimpleThread::~SimpleThread() 131{ 132 delete tc; 133} 134 135void 136SimpleThread::takeOverFrom(ThreadContext *oldContext) 137{ 138 // some things should already be set up 139#if FULL_SYSTEM 140 assert(system == oldContext->getSystemPtr()); 141#else 142 assert(process == oldContext->getProcessPtr()); 143#endif 144 145 copyState(oldContext); 146#if FULL_SYSTEM 147 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 148 if (quiesce) { 149 // Point the quiesce event's TC at this TC so that it wakes up 150 // the proper CPU. 151 quiesce->tc = tc; 152 } 153 if (quiesceEvent) { 154 quiesceEvent->tc = tc; 155 } 156 157 Kernel::Statistics *stats = oldContext->getKernelStats(); 158 if (stats) { 159 kernelStats = stats; 160 } 161#endif 162 163 storeCondFailures = 0; 164 165 oldContext->setStatus(ThreadContext::Unallocated); 166} 167 168void 169SimpleThread::copyTC(ThreadContext *context) 170{ 171 copyState(context); 172 173#if FULL_SYSTEM 174 EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 175 if (quiesce) { 176 quiesceEvent = quiesce; 177 } 178 Kernel::Statistics *stats = context->getKernelStats(); 179 if (stats) { 180 kernelStats = stats; 181 } 182#endif 183} 184 185void 186SimpleThread::copyState(ThreadContext *oldContext) 187{ 188 // copy over functional state 189 _status = oldContext->status(); 190 copyArchRegs(oldContext); 191 cpuId = oldContext->readCpuId(); 192#if !FULL_SYSTEM 193 funcExeInst = oldContext->readFuncExeInst(); 194#endif 195 inst = oldContext->getInst(); 196} 197 198void 199SimpleThread::serialize(ostream &os) 200{ 201 ThreadState::serialize(os); 202 regs.serialize(os); 203 // thread_num and cpu_id are deterministic from the config 204} 205 206 207void 208SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 209{ 210 ThreadState::unserialize(cp, section); 211 regs.unserialize(cp, section); 212 // thread_num and cpu_id are deterministic from the config 213} 214 215#if FULL_SYSTEM 216void 217SimpleThread::dumpFuncProfile() 218{ 219 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 220 profile->dump(tc, *os); 221} 222#endif 223 224void 225SimpleThread::activate(int delay) 226{ 227 if (status() == ThreadContext::Active) 228 return; 229 230 lastActivate = curTick; 231 232 if (status() == ThreadContext::Unallocated) { 233 cpu->activateWhenReady(tid); 234 return; 235 } 236 237 _status = ThreadContext::Active; 238 239 // status() == Suspended 240 cpu->activateContext(tid, delay); 241} 242 243void 244SimpleThread::suspend() 245{ 246 if (status() == ThreadContext::Suspended) 247 return; 248 249 lastActivate = curTick; 250 lastSuspend = curTick; 251/* 252#if FULL_SYSTEM 253 // Don't change the status from active if there are pending interrupts 254 if (cpu->check_interrupts()) { 255 assert(status() == ThreadContext::Active); 256 return; 257 } 258#endif 259*/ 260 _status = ThreadContext::Suspended; 261 cpu->suspendContext(tid); 262} 263 264void 265SimpleThread::deallocate() 266{ 267 if (status() == ThreadContext::Unallocated) 268 return; 269 270 _status = ThreadContext::Unallocated; 271 cpu->deallocateContext(tid); 272} 273 274void 275SimpleThread::halt() 276{ 277 if (status() == ThreadContext::Halted) 278 return; 279 280 _status = ThreadContext::Halted; 281 cpu->haltContext(tid); 282} 283 284 285void 286SimpleThread::regStats(const string &name) 287{ 288#if FULL_SYSTEM 289 if (kernelStats) 290 kernelStats->regStats(name + ".kern"); 291#endif 292} 293 294void 295SimpleThread::copyArchRegs(ThreadContext *src_tc) 296{ 297 TheISA::copyRegs(src_tc, tc); 298} 299 300#if FULL_SYSTEM 301VirtualPort* 302SimpleThread::getVirtPort(ThreadContext *src_tc) 303{ 304 if (!src_tc) 305 return virtPort; 306 307 VirtualPort *vp; 308 Port *mem_port; 309 310 vp = new VirtualPort("tc-vport", src_tc); 311 mem_port = system->physmem->getPort("functional"); 312 mem_port->setPeer(vp); 313 vp->setPeer(mem_port); 314 return vp; 315} 316 317void 318SimpleThread::delVirtPort(VirtualPort *vp) 319{ 320 if (vp != virtPort) { 321 delete vp->getPeer(); 322 delete vp; 323 } 324} 325
| 133#endif 134{ 135 tc = new ProxyThreadContext<SimpleThread>(this); 136 regs.clear(); 137} 138 139SimpleThread::~SimpleThread() 140{ 141 delete tc; 142} 143 144void 145SimpleThread::takeOverFrom(ThreadContext *oldContext) 146{ 147 // some things should already be set up 148#if FULL_SYSTEM 149 assert(system == oldContext->getSystemPtr()); 150#else 151 assert(process == oldContext->getProcessPtr()); 152#endif 153 154 copyState(oldContext); 155#if FULL_SYSTEM 156 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 157 if (quiesce) { 158 // Point the quiesce event's TC at this TC so that it wakes up 159 // the proper CPU. 160 quiesce->tc = tc; 161 } 162 if (quiesceEvent) { 163 quiesceEvent->tc = tc; 164 } 165 166 Kernel::Statistics *stats = oldContext->getKernelStats(); 167 if (stats) { 168 kernelStats = stats; 169 } 170#endif 171 172 storeCondFailures = 0; 173 174 oldContext->setStatus(ThreadContext::Unallocated); 175} 176 177void 178SimpleThread::copyTC(ThreadContext *context) 179{ 180 copyState(context); 181 182#if FULL_SYSTEM 183 EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 184 if (quiesce) { 185 quiesceEvent = quiesce; 186 } 187 Kernel::Statistics *stats = context->getKernelStats(); 188 if (stats) { 189 kernelStats = stats; 190 } 191#endif 192} 193 194void 195SimpleThread::copyState(ThreadContext *oldContext) 196{ 197 // copy over functional state 198 _status = oldContext->status(); 199 copyArchRegs(oldContext); 200 cpuId = oldContext->readCpuId(); 201#if !FULL_SYSTEM 202 funcExeInst = oldContext->readFuncExeInst(); 203#endif 204 inst = oldContext->getInst(); 205} 206 207void 208SimpleThread::serialize(ostream &os) 209{ 210 ThreadState::serialize(os); 211 regs.serialize(os); 212 // thread_num and cpu_id are deterministic from the config 213} 214 215 216void 217SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 218{ 219 ThreadState::unserialize(cp, section); 220 regs.unserialize(cp, section); 221 // thread_num and cpu_id are deterministic from the config 222} 223 224#if FULL_SYSTEM 225void 226SimpleThread::dumpFuncProfile() 227{ 228 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 229 profile->dump(tc, *os); 230} 231#endif 232 233void 234SimpleThread::activate(int delay) 235{ 236 if (status() == ThreadContext::Active) 237 return; 238 239 lastActivate = curTick; 240 241 if (status() == ThreadContext::Unallocated) { 242 cpu->activateWhenReady(tid); 243 return; 244 } 245 246 _status = ThreadContext::Active; 247 248 // status() == Suspended 249 cpu->activateContext(tid, delay); 250} 251 252void 253SimpleThread::suspend() 254{ 255 if (status() == ThreadContext::Suspended) 256 return; 257 258 lastActivate = curTick; 259 lastSuspend = curTick; 260/* 261#if FULL_SYSTEM 262 // Don't change the status from active if there are pending interrupts 263 if (cpu->check_interrupts()) { 264 assert(status() == ThreadContext::Active); 265 return; 266 } 267#endif 268*/ 269 _status = ThreadContext::Suspended; 270 cpu->suspendContext(tid); 271} 272 273void 274SimpleThread::deallocate() 275{ 276 if (status() == ThreadContext::Unallocated) 277 return; 278 279 _status = ThreadContext::Unallocated; 280 cpu->deallocateContext(tid); 281} 282 283void 284SimpleThread::halt() 285{ 286 if (status() == ThreadContext::Halted) 287 return; 288 289 _status = ThreadContext::Halted; 290 cpu->haltContext(tid); 291} 292 293 294void 295SimpleThread::regStats(const string &name) 296{ 297#if FULL_SYSTEM 298 if (kernelStats) 299 kernelStats->regStats(name + ".kern"); 300#endif 301} 302 303void 304SimpleThread::copyArchRegs(ThreadContext *src_tc) 305{ 306 TheISA::copyRegs(src_tc, tc); 307} 308 309#if FULL_SYSTEM 310VirtualPort* 311SimpleThread::getVirtPort(ThreadContext *src_tc) 312{ 313 if (!src_tc) 314 return virtPort; 315 316 VirtualPort *vp; 317 Port *mem_port; 318 319 vp = new VirtualPort("tc-vport", src_tc); 320 mem_port = system->physmem->getPort("functional"); 321 mem_port->setPeer(vp); 322 vp->setPeer(mem_port); 323 return vp; 324} 325 326void 327SimpleThread::delVirtPort(VirtualPort *vp) 328{ 329 if (vp != virtPort) { 330 delete vp->getPeer(); 331 delete vp; 332 } 333} 334
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326#else 327TranslatingPort * 328SimpleThread::getMemPort() 329{ 330 if (port != NULL) 331 return port;
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332
| 335
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333 /* Use this port to for syscall emulation writes to memory. */ 334 Port *dcache_port; 335 port = new TranslatingPort(csprintf("%s-%d-funcport", 336 cpu->name(), tid), 337 process->pTable, false); 338 dcache_port = cpu->getPort("dcache_port"); 339 assert(dcache_port != NULL); 340 dcache_port = dcache_port->getPeer(); 341// mem_port->setPeer(port); 342 port->setPeer(dcache_port); 343 return port; 344} 345
| |
346#endif 347
| 336#endif 337
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