1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/kernel_stats.hh"
38#include "arch/stacktrace.hh"
39#include "arch/utility.hh"
40#include "base/callback.hh"
41#include "base/cprintf.hh"
42#include "base/output.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/base.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/thread_context.hh"
50#include "mem/fs_translating_port_proxy.hh"
51#include "mem/se_translating_port_proxy.hh"
52#include "params/BaseCPU.hh"
53#include "sim/faults.hh"
54#include "sim/full_system.hh"
55#include "sim/process.hh"
56#include "sim/serialize.hh"
57#include "sim/sim_exit.hh"
58#include "sim/system.hh"
59
60using namespace std;
61
62// constructor
63SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
64 Process *_process, TheISA::TLB *_itb,
65 TheISA::TLB *_dtb, TheISA::ISA *_isa)
66 : ThreadState(_cpu, _thread_num, _process), isa(_isa),
67 predicate(false), system(_sys),
68 itb(_itb), dtb(_dtb)
69{
70 clearArchRegs();
71 tc = new ProxyThreadContext<SimpleThread>(this);
72}
73
74SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
75 TheISA::TLB *_itb, TheISA::TLB *_dtb,
76 TheISA::ISA *_isa, bool use_kernel_stats)
77 : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
78 dtb(_dtb)
79{
80 tc = new ProxyThreadContext<SimpleThread>(this);
81
82 quiesceEvent = new EndQuiesceEvent(tc);
83
84 clearArchRegs();
85
86 if (baseCpu->params()->profile) {
87 profile = new FunctionProfile(system->kernelSymtab);
88 Callback *cb =
89 new MakeCallback<SimpleThread,
90 &SimpleThread::dumpFuncProfile>(this);
91 registerExitCallback(cb);
92 }
93
94 // let's fill with a dummy node for now so we don't get a segfault
95 // on the first cycle when there's no node available.
96 static ProfileNode dummyNode;
97 profileNode = &dummyNode;
98 profilePC = 3;
99
100 if (use_kernel_stats)
101 kernelStats = new TheISA::Kernel::Statistics(system);
102}
103
104SimpleThread::~SimpleThread()
105{
106 delete tc;
107}
108
109void
110SimpleThread::takeOverFrom(ThreadContext *oldContext)
111{
112 ::takeOverFrom(*tc, *oldContext);
113 decoder.takeOverFrom(oldContext->getDecoderPtr());
114
115 kernelStats = oldContext->getKernelStats();
116 funcExeInst = oldContext->readFuncExeInst();
117 storeCondFailures = 0;
118}
119
120void
121SimpleThread::copyState(ThreadContext *oldContext)
122{
123 // copy over functional state
124 _status = oldContext->status();
125 copyArchRegs(oldContext);
126 if (FullSystem)
127 funcExeInst = oldContext->readFuncExeInst();
128
129 _threadId = oldContext->threadId();
130 _contextId = oldContext->contextId();
131}
132
133void
134SimpleThread::serialize(CheckpointOut &cp) const
135{
136 ThreadState::serialize(cp);
137 ::serialize(*tc, cp);
138}
139
140
141void
142SimpleThread::unserialize(CheckpointIn &cp)
143{
144 ThreadState::unserialize(cp);
145 ::unserialize(*tc, cp);
146}
147
148void
149SimpleThread::startup()
150{
151 isa->startup(tc);
152}
153
154void
155SimpleThread::dumpFuncProfile()
156{
| 1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/kernel_stats.hh"
38#include "arch/stacktrace.hh"
39#include "arch/utility.hh"
40#include "base/callback.hh"
41#include "base/cprintf.hh"
42#include "base/output.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/base.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/thread_context.hh"
50#include "mem/fs_translating_port_proxy.hh"
51#include "mem/se_translating_port_proxy.hh"
52#include "params/BaseCPU.hh"
53#include "sim/faults.hh"
54#include "sim/full_system.hh"
55#include "sim/process.hh"
56#include "sim/serialize.hh"
57#include "sim/sim_exit.hh"
58#include "sim/system.hh"
59
60using namespace std;
61
62// constructor
63SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
64 Process *_process, TheISA::TLB *_itb,
65 TheISA::TLB *_dtb, TheISA::ISA *_isa)
66 : ThreadState(_cpu, _thread_num, _process), isa(_isa),
67 predicate(false), system(_sys),
68 itb(_itb), dtb(_dtb)
69{
70 clearArchRegs();
71 tc = new ProxyThreadContext<SimpleThread>(this);
72}
73
74SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
75 TheISA::TLB *_itb, TheISA::TLB *_dtb,
76 TheISA::ISA *_isa, bool use_kernel_stats)
77 : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
78 dtb(_dtb)
79{
80 tc = new ProxyThreadContext<SimpleThread>(this);
81
82 quiesceEvent = new EndQuiesceEvent(tc);
83
84 clearArchRegs();
85
86 if (baseCpu->params()->profile) {
87 profile = new FunctionProfile(system->kernelSymtab);
88 Callback *cb =
89 new MakeCallback<SimpleThread,
90 &SimpleThread::dumpFuncProfile>(this);
91 registerExitCallback(cb);
92 }
93
94 // let's fill with a dummy node for now so we don't get a segfault
95 // on the first cycle when there's no node available.
96 static ProfileNode dummyNode;
97 profileNode = &dummyNode;
98 profilePC = 3;
99
100 if (use_kernel_stats)
101 kernelStats = new TheISA::Kernel::Statistics(system);
102}
103
104SimpleThread::~SimpleThread()
105{
106 delete tc;
107}
108
109void
110SimpleThread::takeOverFrom(ThreadContext *oldContext)
111{
112 ::takeOverFrom(*tc, *oldContext);
113 decoder.takeOverFrom(oldContext->getDecoderPtr());
114
115 kernelStats = oldContext->getKernelStats();
116 funcExeInst = oldContext->readFuncExeInst();
117 storeCondFailures = 0;
118}
119
120void
121SimpleThread::copyState(ThreadContext *oldContext)
122{
123 // copy over functional state
124 _status = oldContext->status();
125 copyArchRegs(oldContext);
126 if (FullSystem)
127 funcExeInst = oldContext->readFuncExeInst();
128
129 _threadId = oldContext->threadId();
130 _contextId = oldContext->contextId();
131}
132
133void
134SimpleThread::serialize(CheckpointOut &cp) const
135{
136 ThreadState::serialize(cp);
137 ::serialize(*tc, cp);
138}
139
140
141void
142SimpleThread::unserialize(CheckpointIn &cp)
143{
144 ThreadState::unserialize(cp);
145 ::unserialize(*tc, cp);
146}
147
148void
149SimpleThread::startup()
150{
151 isa->startup(tc);
152}
153
154void
155SimpleThread::dumpFuncProfile()
156{
|