1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/kernel_stats.hh"
38#include "arch/stacktrace.hh"
39#include "arch/utility.hh"
40#include "base/callback.hh"
41#include "base/cprintf.hh"
42#include "base/output.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/base.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/thread_context.hh"
50#include "mem/fs_translating_port_proxy.hh"
51#include "mem/se_translating_port_proxy.hh"
52#include "params/BaseCPU.hh"
53#include "sim/faults.hh"
54#include "sim/full_system.hh"
55#include "sim/process.hh"
56#include "sim/serialize.hh"
57#include "sim/sim_exit.hh"
58#include "sim/system.hh"
59
60using namespace std;
61
62// constructor
63SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
64 Process *_process, TheISA::TLB *_itb,
65 TheISA::TLB *_dtb, TheISA::ISA *_isa)
| 1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/kernel_stats.hh"
38#include "arch/stacktrace.hh"
39#include "arch/utility.hh"
40#include "base/callback.hh"
41#include "base/cprintf.hh"
42#include "base/output.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/base.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/thread_context.hh"
50#include "mem/fs_translating_port_proxy.hh"
51#include "mem/se_translating_port_proxy.hh"
52#include "params/BaseCPU.hh"
53#include "sim/faults.hh"
54#include "sim/full_system.hh"
55#include "sim/process.hh"
56#include "sim/serialize.hh"
57#include "sim/sim_exit.hh"
58#include "sim/system.hh"
59
60using namespace std;
61
62// constructor
63SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
64 Process *_process, TheISA::TLB *_itb,
65 TheISA::TLB *_dtb, TheISA::ISA *_isa)
|
66 : ThreadState(_cpu, _thread_num, _process), isa(_isa), system(_sys),
| 66 : ThreadState(_cpu, _thread_num, _process), isa(_isa),
67 predicate(false), system(_sys),
|
67 itb(_itb), dtb(_dtb)
68{
69 clearArchRegs();
70 tc = new ProxyThreadContext<SimpleThread>(this);
71}
72
73SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
74 TheISA::TLB *_itb, TheISA::TLB *_dtb,
75 TheISA::ISA *_isa, bool use_kernel_stats)
76 : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
77 dtb(_dtb)
78{
79 tc = new ProxyThreadContext<SimpleThread>(this);
80
81 quiesceEvent = new EndQuiesceEvent(tc);
82
83 clearArchRegs();
84
85 if (baseCpu->params()->profile) {
86 profile = new FunctionProfile(system->kernelSymtab);
87 Callback *cb =
88 new MakeCallback<SimpleThread,
89 &SimpleThread::dumpFuncProfile>(this);
90 registerExitCallback(cb);
91 }
92
93 // let's fill with a dummy node for now so we don't get a segfault
94 // on the first cycle when there's no node available.
95 static ProfileNode dummyNode;
96 profileNode = &dummyNode;
97 profilePC = 3;
98
99 if (use_kernel_stats)
100 kernelStats = new TheISA::Kernel::Statistics(system);
101}
102
103SimpleThread::~SimpleThread()
104{
105 delete tc;
106}
107
108void
109SimpleThread::takeOverFrom(ThreadContext *oldContext)
110{
111 ::takeOverFrom(*tc, *oldContext);
112 decoder.takeOverFrom(oldContext->getDecoderPtr());
113
114 kernelStats = oldContext->getKernelStats();
115 funcExeInst = oldContext->readFuncExeInst();
116 storeCondFailures = 0;
117}
118
119void
120SimpleThread::copyState(ThreadContext *oldContext)
121{
122 // copy over functional state
123 _status = oldContext->status();
124 copyArchRegs(oldContext);
125 if (FullSystem)
126 funcExeInst = oldContext->readFuncExeInst();
127
128 _threadId = oldContext->threadId();
129 _contextId = oldContext->contextId();
130}
131
132void
133SimpleThread::serialize(ostream &os)
134{
135 ThreadState::serialize(os);
136 ::serialize(*tc, os);
137}
138
139
140void
141SimpleThread::unserialize(Checkpoint *cp, const std::string §ion)
142{
143 ThreadState::unserialize(cp, section);
144 ::unserialize(*tc, cp, section);
145}
146
147void
148SimpleThread::startup()
149{
150 isa->startup(tc);
151}
152
153void
154SimpleThread::dumpFuncProfile()
155{
156 std::ostream *os = simout.create(csprintf("profile.%s.dat",
157 baseCpu->name()));
158 profile->dump(tc, *os);
159}
160
161void
162SimpleThread::activate()
163{
164 if (status() == ThreadContext::Active)
165 return;
166
167 lastActivate = curTick();
168 _status = ThreadContext::Active;
169 baseCpu->activateContext(_threadId);
170}
171
172void
173SimpleThread::suspend()
174{
175 if (status() == ThreadContext::Suspended)
176 return;
177
178 lastActivate = curTick();
179 lastSuspend = curTick();
180 _status = ThreadContext::Suspended;
181 baseCpu->suspendContext(_threadId);
182}
183
184
185void
186SimpleThread::halt()
187{
188 if (status() == ThreadContext::Halted)
189 return;
190
191 _status = ThreadContext::Halted;
192 baseCpu->haltContext(_threadId);
193}
194
195
196void
197SimpleThread::regStats(const string &name)
198{
199 if (FullSystem && kernelStats)
200 kernelStats->regStats(name + ".kern");
201}
202
203void
204SimpleThread::copyArchRegs(ThreadContext *src_tc)
205{
206 TheISA::copyRegs(src_tc, tc);
207}
208
209// The following methods are defined in src/arch/alpha/ev5.cc for
210// Alpha.
211#if THE_ISA != ALPHA_ISA
212Fault
213SimpleThread::hwrei()
214{
215 return NoFault;
216}
217
218bool
219SimpleThread::simPalCheck(int palFunc)
220{
221 return true;
222}
223#endif
| 68 itb(_itb), dtb(_dtb)
69{
70 clearArchRegs();
71 tc = new ProxyThreadContext<SimpleThread>(this);
72}
73
74SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
75 TheISA::TLB *_itb, TheISA::TLB *_dtb,
76 TheISA::ISA *_isa, bool use_kernel_stats)
77 : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
78 dtb(_dtb)
79{
80 tc = new ProxyThreadContext<SimpleThread>(this);
81
82 quiesceEvent = new EndQuiesceEvent(tc);
83
84 clearArchRegs();
85
86 if (baseCpu->params()->profile) {
87 profile = new FunctionProfile(system->kernelSymtab);
88 Callback *cb =
89 new MakeCallback<SimpleThread,
90 &SimpleThread::dumpFuncProfile>(this);
91 registerExitCallback(cb);
92 }
93
94 // let's fill with a dummy node for now so we don't get a segfault
95 // on the first cycle when there's no node available.
96 static ProfileNode dummyNode;
97 profileNode = &dummyNode;
98 profilePC = 3;
99
100 if (use_kernel_stats)
101 kernelStats = new TheISA::Kernel::Statistics(system);
102}
103
104SimpleThread::~SimpleThread()
105{
106 delete tc;
107}
108
109void
110SimpleThread::takeOverFrom(ThreadContext *oldContext)
111{
112 ::takeOverFrom(*tc, *oldContext);
113 decoder.takeOverFrom(oldContext->getDecoderPtr());
114
115 kernelStats = oldContext->getKernelStats();
116 funcExeInst = oldContext->readFuncExeInst();
117 storeCondFailures = 0;
118}
119
120void
121SimpleThread::copyState(ThreadContext *oldContext)
122{
123 // copy over functional state
124 _status = oldContext->status();
125 copyArchRegs(oldContext);
126 if (FullSystem)
127 funcExeInst = oldContext->readFuncExeInst();
128
129 _threadId = oldContext->threadId();
130 _contextId = oldContext->contextId();
131}
132
133void
134SimpleThread::serialize(ostream &os)
135{
136 ThreadState::serialize(os);
137 ::serialize(*tc, os);
138}
139
140
141void
142SimpleThread::unserialize(Checkpoint *cp, const std::string §ion)
143{
144 ThreadState::unserialize(cp, section);
145 ::unserialize(*tc, cp, section);
146}
147
148void
149SimpleThread::startup()
150{
151 isa->startup(tc);
152}
153
154void
155SimpleThread::dumpFuncProfile()
156{
157 std::ostream *os = simout.create(csprintf("profile.%s.dat",
158 baseCpu->name()));
159 profile->dump(tc, *os);
160}
161
162void
163SimpleThread::activate()
164{
165 if (status() == ThreadContext::Active)
166 return;
167
168 lastActivate = curTick();
169 _status = ThreadContext::Active;
170 baseCpu->activateContext(_threadId);
171}
172
173void
174SimpleThread::suspend()
175{
176 if (status() == ThreadContext::Suspended)
177 return;
178
179 lastActivate = curTick();
180 lastSuspend = curTick();
181 _status = ThreadContext::Suspended;
182 baseCpu->suspendContext(_threadId);
183}
184
185
186void
187SimpleThread::halt()
188{
189 if (status() == ThreadContext::Halted)
190 return;
191
192 _status = ThreadContext::Halted;
193 baseCpu->haltContext(_threadId);
194}
195
196
197void
198SimpleThread::regStats(const string &name)
199{
200 if (FullSystem && kernelStats)
201 kernelStats->regStats(name + ".kern");
202}
203
204void
205SimpleThread::copyArchRegs(ThreadContext *src_tc)
206{
207 TheISA::copyRegs(src_tc, tc);
208}
209
210// The following methods are defined in src/arch/alpha/ev5.cc for
211// Alpha.
212#if THE_ISA != ALPHA_ISA
213Fault
214SimpleThread::hwrei()
215{
216 return NoFault;
217}
218
219bool
220SimpleThread::simPalCheck(int palFunc)
221{
222 return true;
223}
224#endif
|