1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/utility.hh"
38#include "config/the_isa.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/thread_context.hh"
42#include "mem/vport.hh"
43#include "params/BaseCPU.hh"
44
45#if FULL_SYSTEM
46#include "arch/kernel_stats.hh"
47#include "arch/stacktrace.hh"
48#include "base/callback.hh"
49#include "base/cprintf.hh"
50#include "base/output.hh"
51#include "base/trace.hh"
52#include "cpu/profile.hh"
53#include "cpu/quiesce_event.hh"
54#include "sim/serialize.hh"
55#include "sim/sim_exit.hh"
56#else
57#include "mem/translating_port.hh"
58#include "sim/process.hh"
59#include "sim/system.hh"
60#endif
61
62using namespace std;
63
64// constructor
65#if FULL_SYSTEM
66SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
67 TheISA::TLB *_itb, TheISA::TLB *_dtb,
68 bool use_kernel_stats)
69 : ThreadState(_cpu, _thread_num),
70 cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb)
71
72{
73 tc = new ProxyThreadContext<SimpleThread>(this);
74
75 quiesceEvent = new EndQuiesceEvent(tc);
76
77 clearArchRegs();
78
79 if (cpu->params()->profile) {
80 profile = new FunctionProfile(system->kernelSymtab);
81 Callback *cb =
82 new MakeCallback<SimpleThread,
83 &SimpleThread::dumpFuncProfile>(this);
84 registerExitCallback(cb);
85 }
86
87 // let's fill with a dummy node for now so we don't get a segfault
88 // on the first cycle when there's no node available.
89 static ProfileNode dummyNode;
90 profileNode = &dummyNode;
91 profilePC = 3;
92
93 if (use_kernel_stats)
94 kernelStats = new TheISA::Kernel::Statistics(system);
95}
96#else
97SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
98 TheISA::TLB *_itb, TheISA::TLB *_dtb)
99 : ThreadState(_cpu, _thread_num, _process),
100 cpu(_cpu), itb(_itb), dtb(_dtb)
101{
102 clearArchRegs();
103 tc = new ProxyThreadContext<SimpleThread>(this);
104}
105
106#endif
107
108SimpleThread::SimpleThread()
109#if FULL_SYSTEM
110 : ThreadState(NULL, -1)
111#else
112 : ThreadState(NULL, -1, NULL)
113#endif
114{
115 tc = new ProxyThreadContext<SimpleThread>(this);
116}
117
118SimpleThread::~SimpleThread()
119{
120 delete physPort;
121 delete virtPort;
122 delete tc;
123}
124
125void
126SimpleThread::takeOverFrom(ThreadContext *oldContext)
127{
128 // some things should already be set up
129#if FULL_SYSTEM
130 assert(system == oldContext->getSystemPtr());
131#else
132 assert(process == oldContext->getProcessPtr());
133#endif
134
135 copyState(oldContext);
136#if FULL_SYSTEM
137 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
138 if (quiesce) {
139 // Point the quiesce event's TC at this TC so that it wakes up
140 // the proper CPU.
141 quiesce->tc = tc;
142 }
143 if (quiesceEvent) {
144 quiesceEvent->tc = tc;
145 }
146
147 TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
148 if (stats) {
149 kernelStats = stats;
150 }
151#endif
152
153 storeCondFailures = 0;
154
155 oldContext->setStatus(ThreadContext::Halted);
156}
157
158void
159SimpleThread::copyTC(ThreadContext *context)
160{
161 copyState(context);
162
163#if FULL_SYSTEM
164 EndQuiesceEvent *quiesce = context->getQuiesceEvent();
165 if (quiesce) {
166 quiesceEvent = quiesce;
167 }
168 TheISA::Kernel::Statistics *stats = context->getKernelStats();
169 if (stats) {
170 kernelStats = stats;
171 }
172#endif
173}
174
175void
176SimpleThread::copyState(ThreadContext *oldContext)
177{
178 // copy over functional state
179 _status = oldContext->status();
180 copyArchRegs(oldContext);
181#if !FULL_SYSTEM
182 funcExeInst = oldContext->readFuncExeInst();
183#endif
184
185 _threadId = oldContext->threadId();
186 _contextId = oldContext->contextId();
187}
188
189void
190SimpleThread::serialize(ostream &os)
191{
192 ThreadState::serialize(os);
193 SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
194 SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
195 _pcState.serialize(os);
196 // thread_num and cpu_id are deterministic from the config
197
198 //
199 // Now must serialize all the ISA dependent state
200 //
201 isa.serialize(cpu, os);
202}
203
204
205void
206SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
207{
208 ThreadState::unserialize(cp, section);
209 UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
210 UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
211 _pcState.unserialize(cp, section);
212 // thread_num and cpu_id are deterministic from the config
213
214 //
215 // Now must unserialize all the ISA dependent state
216 //
217 isa.unserialize(cpu, cp, section);
218}
219
220#if FULL_SYSTEM
221void
222SimpleThread::dumpFuncProfile()
223{
224 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
225 profile->dump(tc, *os);
226}
227#endif
228
229void
230SimpleThread::activate(int delay)
231{
232 if (status() == ThreadContext::Active)
233 return;
234
235 lastActivate = curTick();
236
237// if (status() == ThreadContext::Unallocated) {
238// cpu->activateWhenReady(_threadId);
239// return;
240// }
241
242 _status = ThreadContext::Active;
243
244 // status() == Suspended
245 cpu->activateContext(_threadId, delay);
246}
247
248void
249SimpleThread::suspend()
250{
251 if (status() == ThreadContext::Suspended)
252 return;
253
254 lastActivate = curTick();
255 lastSuspend = curTick();
256/*
257#if FULL_SYSTEM
258 // Don't change the status from active if there are pending interrupts
259 if (cpu->checkInterrupts()) {
260 assert(status() == ThreadContext::Active);
261 return;
262 }
263#endif
264*/
265 _status = ThreadContext::Suspended;
266 cpu->suspendContext(_threadId);
267}
268
269
270void
271SimpleThread::halt()
272{
273 if (status() == ThreadContext::Halted)
274 return;
275
276 _status = ThreadContext::Halted;
277 cpu->haltContext(_threadId);
278}
279
280
281void
282SimpleThread::regStats(const string &name)
283{
284#if FULL_SYSTEM
285 if (kernelStats)
286 kernelStats->regStats(name + ".kern");
287#endif
288}
289
290void
291SimpleThread::copyArchRegs(ThreadContext *src_tc)
292{
293 TheISA::copyRegs(src_tc, tc);
294}
295