timing.hh (9840:c562aa658a6f) timing.hh (10030:b531e328342d)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 151 unchanged lines hidden (view full) ---

160 : MasterPort(_name, _cpu), cpu(_cpu), retryEvent(this)
161 { }
162
163 protected:
164
165 /**
166 * Snooping a coherence request, do nothing.
167 */
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 151 unchanged lines hidden (view full) ---

160 : MasterPort(_name, _cpu), cpu(_cpu), retryEvent(this)
161 { }
162
163 protected:
164
165 /**
166 * Snooping a coherence request, do nothing.
167 */
168 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
168 virtual void recvTimingSnoopReq(PacketPtr pkt) {}
169
170 TimingSimpleCPU* cpu;
171
172 struct TickEvent : public Event
173 {
174 PacketPtr pkt;
175 TimingSimpleCPU *cpu;
176

--- 35 unchanged lines hidden (view full) ---

212
213 class DcachePort : public TimingCPUPort
214 {
215 public:
216
217 DcachePort(TimingSimpleCPU *_cpu)
218 : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
219 tickEvent(_cpu)
169
170 TimingSimpleCPU* cpu;
171
172 struct TickEvent : public Event
173 {
174 PacketPtr pkt;
175 TimingSimpleCPU *cpu;
176

--- 35 unchanged lines hidden (view full) ---

212
213 class DcachePort : public TimingCPUPort
214 {
215 public:
216
217 DcachePort(TimingSimpleCPU *_cpu)
218 : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
219 tickEvent(_cpu)
220 { }
220 {
221 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
222 }
221
223
224 Addr cacheBlockMask;
222 protected:
223
225 protected:
226
227 /** Snoop a coherence request, we need to check if this causes
228 * a wakeup event on a cpu that is monitoring an address
229 */
230 virtual void recvTimingSnoopReq(PacketPtr pkt);
231
224 virtual bool recvTimingResp(PacketPtr pkt);
225
226 virtual void recvRetry();
227
228 struct DTickEvent : public TickEvent
229 {
230 DTickEvent(TimingSimpleCPU *_cpu)
231 : TickEvent(_cpu) {}

--- 117 unchanged lines hidden ---
232 virtual bool recvTimingResp(PacketPtr pkt);
233
234 virtual void recvRetry();
235
236 struct DTickEvent : public TickEvent
237 {
238 DTickEvent(TimingSimpleCPU *_cpu)
239 : TickEvent(_cpu) {}

--- 117 unchanged lines hidden ---