timing.hh (9523:b8c8437f71d9) timing.hh (9608:e2b6b86fda03)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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147 bool handleWritePacket();
148
149 /**
150 * A TimingCPUPort overrides the default behaviour of the
151 * recvTiming and recvRetry and implements events for the
152 * scheduling of handling of incoming packets in the following
153 * cycle.
154 */
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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147 bool handleWritePacket();
148
149 /**
150 * A TimingCPUPort overrides the default behaviour of the
151 * recvTiming and recvRetry and implements events for the
152 * scheduling of handling of incoming packets in the following
153 * cycle.
154 */
155 class TimingCPUPort : public CpuPort
155 class TimingCPUPort : public MasterPort
156 {
157 public:
158
159 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
156 {
157 public:
158
159 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
160 : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this)
160 : MasterPort(_name, _cpu), cpu(_cpu), retryEvent(this)
161 { }
162
163 protected:
164
165 /**
166 * Snooping a coherence request, do nothing.
167 */
168 virtual void recvTimingSnoopReq(PacketPtr pkt) { }

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243 PacketPtr ifetch_pkt;
244 PacketPtr dcache_pkt;
245
246 Tick previousCycle;
247
248 protected:
249
250 /** Return a reference to the data port. */
161 { }
162
163 protected:
164
165 /**
166 * Snooping a coherence request, do nothing.
167 */
168 virtual void recvTimingSnoopReq(PacketPtr pkt) { }

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243 PacketPtr ifetch_pkt;
244 PacketPtr dcache_pkt;
245
246 Tick previousCycle;
247
248 protected:
249
250 /** Return a reference to the data port. */
251 virtual CpuPort &getDataPort() { return dcachePort; }
251 virtual MasterPort &getDataPort() { return dcachePort; }
252
253 /** Return a reference to the instruction port. */
252
253 /** Return a reference to the instruction port. */
254 virtual CpuPort &getInstPort() { return icachePort; }
254 virtual MasterPort &getInstPort() { return icachePort; }
255
256 public:
257
258 unsigned int drain(DrainManager *drain_manager);
259 void drainResume();
260
261 void switchOut();
262 void takeOverFrom(BaseCPU *oldCPU);

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256 public:
257
258 unsigned int drain(DrainManager *drain_manager);
259 void drainResume();
260
261 void switchOut();
262 void takeOverFrom(BaseCPU *oldCPU);

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