timing.hh (9342:6fec8f26e56d) timing.hh (9442:36967173340c)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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39{
40 public:
41
42 TimingSimpleCPU(TimingSimpleCPUParams * params);
43 virtual ~TimingSimpleCPU();
44
45 virtual void init();
46
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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51{
52 public:
53
54 TimingSimpleCPU(TimingSimpleCPUParams * params);
55 virtual ~TimingSimpleCPU();
56
57 virtual void init();
58
47 public:
48 DrainManager *drainManager;
49
50 private:
51
52 /*
53 * If an access needs to be broken into fragments, currently at most two,
54 * the the following two classes are used as the sender state of the
55 * packets so the CPU can keep track of everything. In the main packet
56 * sender state, there's an array with a spot for each fragment. If a
57 * fragment has already been accepted by the CPU, aka isn't waiting for

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241 /** Return a reference to the data port. */
242 virtual CpuPort &getDataPort() { return dcachePort; }
243
244 /** Return a reference to the instruction port. */
245 virtual CpuPort &getInstPort() { return icachePort; }
246
247 public:
248
59 private:
60
61 /*
62 * If an access needs to be broken into fragments, currently at most two,
63 * the the following two classes are used as the sender state of the
64 * packets so the CPU can keep track of everything. In the main packet
65 * sender state, there's an array with a spot for each fragment. If a
66 * fragment has already been accepted by the CPU, aka isn't waiting for

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250 /** Return a reference to the data port. */
251 virtual CpuPort &getDataPort() { return dcachePort; }
252
253 /** Return a reference to the instruction port. */
254 virtual CpuPort &getInstPort() { return icachePort; }
255
256 public:
257
249 virtual void serialize(std::ostream &os);
250 virtual void unserialize(Checkpoint *cp, const std::string &section);
251
252 unsigned int drain(DrainManager *drain_manager);
253 void drainResume();
254
255 void switchOut();
256 void takeOverFrom(BaseCPU *oldCPU);
257
258 virtual void activateContext(ThreadID thread_num, Cycles delay);
259 virtual void suspendContext(ThreadID thread_num);

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297 struct IprEvent : Event {
298 Packet *pkt;
299 TimingSimpleCPU *cpu;
300 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
301 virtual void process();
302 virtual const char *description() const;
303 };
304
258 unsigned int drain(DrainManager *drain_manager);
259 void drainResume();
260
261 void switchOut();
262 void takeOverFrom(BaseCPU *oldCPU);
263
264 virtual void activateContext(ThreadID thread_num, Cycles delay);
265 virtual void suspendContext(ThreadID thread_num);

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303 struct IprEvent : Event {
304 Packet *pkt;
305 TimingSimpleCPU *cpu;
306 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
307 virtual void process();
308 virtual const char *description() const;
309 };
310
305 void completeDrain();
311 /**
312 * Check if a system is in a drained state.
313 *
314 * We need to drain if:
315 * <ul>
316 * <li>We are in the middle of a microcode sequence as some CPUs
317 * (e.g., HW accelerated CPUs) can't be started in the middle
318 * of a gem5 microcode sequence.
319 *
320 * <li>Stay at PC is true.
321 * </ul>
322 */
323 bool isDrained() {
324 return microPC() == 0 &&
325 !stayAtPC;
326 }
327
328 /**
329 * Try to complete a drain request.
330 *
331 * @returns true if the CPU is drained, false otherwise.
332 */
333 bool tryCompleteDrain();
334
335 /**
336 * Drain manager to use when signaling drain completion
337 *
338 * This pointer is non-NULL when draining and NULL otherwise.
339 */
340 DrainManager *drainManager;
306};
307
308#endif // __CPU_SIMPLE_TIMING_HH__
341};
342
343#endif // __CPU_SIMPLE_TIMING_HH__