timing.hh (9087:b5a084a6159b) | timing.hh (9095:0e6bd7082fac) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 164 unchanged lines hidden (view full) --- 173 EventWrapper<MasterPort, &MasterPort::sendRetry> retryEvent; 174 }; 175 176 class IcachePort : public TimingCPUPort 177 { 178 public: 179 180 IcachePort(TimingSimpleCPU *_cpu) | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 164 unchanged lines hidden (view full) --- 173 EventWrapper<MasterPort, &MasterPort::sendRetry> retryEvent; 174 }; 175 176 class IcachePort : public TimingCPUPort 177 { 178 public: 179 180 IcachePort(TimingSimpleCPU *_cpu) |
181 : TimingCPUPort(_cpu->name() + "-iport", _cpu), | 181 : TimingCPUPort(_cpu->name() + ".icache_port", _cpu), |
182 tickEvent(_cpu) 183 { } 184 185 protected: 186 187 virtual bool recvTimingResp(PacketPtr pkt); 188 189 virtual void recvRetry(); --- 11 unchanged lines hidden (view full) --- 201 202 }; 203 204 class DcachePort : public TimingCPUPort 205 { 206 public: 207 208 DcachePort(TimingSimpleCPU *_cpu) | 182 tickEvent(_cpu) 183 { } 184 185 protected: 186 187 virtual bool recvTimingResp(PacketPtr pkt); 188 189 virtual void recvRetry(); --- 11 unchanged lines hidden (view full) --- 201 202 }; 203 204 class DcachePort : public TimingCPUPort 205 { 206 public: 207 208 DcachePort(TimingSimpleCPU *_cpu) |
209 : TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu) | 209 : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu), 210 tickEvent(_cpu) |
210 { } 211 212 protected: 213 214 virtual bool recvTimingResp(PacketPtr pkt); 215 216 virtual void recvRetry(); 217 --- 82 unchanged lines hidden --- | 211 { } 212 213 protected: 214 215 virtual bool recvTimingResp(PacketPtr pkt); 216 217 virtual void recvRetry(); 218 --- 82 unchanged lines hidden --- |