timing.hh (8706:b1838faf3bcc) timing.hh (8707:489489c67fd9)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 123 unchanged lines hidden (view full) ---

132 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
133 RequestPtr req1, RequestPtr req2, RequestPtr req,
134 uint8_t *data, bool read);
135
136 bool handleReadPacket(PacketPtr pkt);
137 // This function always implicitly uses dcache_pkt.
138 bool handleWritePacket();
139
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 123 unchanged lines hidden (view full) ---

132 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
133 RequestPtr req1, RequestPtr req2, RequestPtr req,
134 uint8_t *data, bool read);
135
136 bool handleReadPacket(PacketPtr pkt);
137 // This function always implicitly uses dcache_pkt.
138 bool handleWritePacket();
139
140 class CpuPort : public Port
140 /**
141 * A TimingCPUPort overrides the default behaviour of the
142 * recvTiming and recvRetry and implements events for the
143 * scheduling of handling of incoming packets in the following
144 * cycle.
145 */
146 class TimingCPUPort : public CpuPort
141 {
147 {
142 protected:
143 TimingSimpleCPU *cpu;
144 Tick lat;
145
146 public:
147
148 public:
149
148 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
149 : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
150 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
151 : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this)
150 { }
151
152 { }
153
152 bool snoopRangeSent;
153
154 protected:
155
154 protected:
155
156 virtual Tick recvAtomic(PacketPtr pkt);
156 TimingSimpleCPU* cpu;
157
157
158 virtual void recvFunctional(PacketPtr pkt);
159
160 virtual void recvStatusChange(Status status);
161
162 virtual void getDeviceAddressRanges(AddrRangeList &resp,
163 bool &snoop)
164 { resp.clear(); snoop = false; }
165
166 struct TickEvent : public Event
167 {
168 PacketPtr pkt;
169 TimingSimpleCPU *cpu;
170 CpuPort *port;
171
158 struct TickEvent : public Event
159 {
160 PacketPtr pkt;
161 TimingSimpleCPU *cpu;
162 CpuPort *port;
163
172 TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
164 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
173 const char *description() const { return "Timing CPU tick"; }
174 void schedule(PacketPtr _pkt, Tick t);
175 };
176
177 EventWrapper<Port, &Port::sendRetry> retryEvent;
178 };
179
165 const char *description() const { return "Timing CPU tick"; }
166 void schedule(PacketPtr _pkt, Tick t);
167 };
168
169 EventWrapper<Port, &Port::sendRetry> retryEvent;
170 };
171
180 class IcachePort : public CpuPort
172 class IcachePort : public TimingCPUPort
181 {
182 public:
183
173 {
174 public:
175
184 IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
185 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
176 IcachePort(TimingSimpleCPU *_cpu)
177 : TimingCPUPort(_cpu->name() + "-iport", _cpu),
178 tickEvent(_cpu)
186 { }
187
188 protected:
189
190 virtual bool recvTiming(PacketPtr pkt);
191
192 virtual void recvRetry();
193

--- 5 unchanged lines hidden (view full) ---

199 void process();
200 const char *description() const { return "Timing CPU icache tick"; }
201 };
202
203 ITickEvent tickEvent;
204
205 };
206
179 { }
180
181 protected:
182
183 virtual bool recvTiming(PacketPtr pkt);
184
185 virtual void recvRetry();
186

--- 5 unchanged lines hidden (view full) ---

192 void process();
193 const char *description() const { return "Timing CPU icache tick"; }
194 };
195
196 ITickEvent tickEvent;
197
198 };
199
207 class DcachePort : public CpuPort
200 class DcachePort : public TimingCPUPort
208 {
209 public:
210
201 {
202 public:
203
211 DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
212 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
204 DcachePort(TimingSimpleCPU *_cpu)
205 : TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu)
213 { }
214
215 protected:
216
217 virtual bool recvTiming(PacketPtr pkt);
218
219 virtual void recvRetry();
220

--- 76 unchanged lines hidden --- 		206 { }
207
208 protected:
209
210 virtual bool recvTiming(PacketPtr pkt);
211
212 virtual void recvRetry();
213

--- 76 unchanged lines hidden ---