timing.hh (8229:78bf55f23338) | timing.hh (8443:530ff1bc8d70) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 242 unchanged lines hidden (view full) --- 251 virtual void resume(); 252 253 void switchOut(); 254 void takeOverFrom(BaseCPU *oldCPU); 255 256 virtual void activateContext(int thread_num, int delay); 257 virtual void suspendContext(int thread_num); 258 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 242 unchanged lines hidden (view full) --- 251 virtual void resume(); 252 253 void switchOut(); 254 void takeOverFrom(BaseCPU *oldCPU); 255 256 virtual void activateContext(int thread_num, int delay); 257 virtual void suspendContext(int thread_num); 258 |
259 template <class T> 260 Fault read(Addr addr, T &data, unsigned flags); 261 | |
262 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); 263 | 259 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); 260 |
264 template <class T> 265 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 266 | |
267 Fault writeBytes(uint8_t *data, unsigned size, 268 Addr addr, unsigned flags, uint64_t *res); 269 270 void fetch(); 271 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc); 272 void completeIfetch(PacketPtr ); 273 void completeDataAccess(PacketPtr pkt); 274 void advanceInst(Fault fault); --- 7 unchanged lines hidden (view full) --- 282 /** 283 * Finish a DTB translation. 284 * @param state The DTB translation state. 285 */ 286 void finishTranslation(WholeTranslationState *state); 287 288 private: 289 | 261 Fault writeBytes(uint8_t *data, unsigned size, 262 Addr addr, unsigned flags, uint64_t *res); 263 264 void fetch(); 265 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc); 266 void completeIfetch(PacketPtr ); 267 void completeDataAccess(PacketPtr pkt); 268 void advanceInst(Fault fault); --- 7 unchanged lines hidden (view full) --- 276 /** 277 * Finish a DTB translation. 278 * @param state The DTB translation state. 279 */ 280 void finishTranslation(WholeTranslationState *state); 281 282 private: 283 |
290 // The backend for writeBytes and write. It's the same as writeBytes, but 291 // doesn't make a copy of data. 292 Fault writeTheseBytes(uint8_t *data, unsigned size, 293 Addr addr, unsigned flags, uint64_t *res); 294 | |
295 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 296 FetchEvent fetchEvent; 297 298 struct IprEvent : Event { 299 Packet *pkt; 300 TimingSimpleCPU *cpu; 301 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 302 virtual void process(); 303 virtual const char *description() const; 304 }; 305 306 void completeDrain(); 307}; 308 309#endif // __CPU_SIMPLE_TIMING_HH__ | 284 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 285 FetchEvent fetchEvent; 286 287 struct IprEvent : Event { 288 Packet *pkt; 289 TimingSimpleCPU *cpu; 290 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 291 virtual void process(); 292 virtual const char *description() const; 293 }; 294 295 void completeDrain(); 296}; 297 298#endif // __CPU_SIMPLE_TIMING_HH__ |