timing.hh (6973:a123bd350935) timing.hh (7520:67c670459d01)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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246 void takeOverFrom(BaseCPU *oldCPU);
247
248 virtual void activateContext(int thread_num, int delay);
249 virtual void suspendContext(int thread_num);
250
251 template <class T>
252 Fault read(Addr addr, T &data, unsigned flags);
253
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 237 unchanged lines hidden (view full) ---

246 void takeOverFrom(BaseCPU *oldCPU);
247
248 virtual void activateContext(int thread_num, int delay);
249 virtual void suspendContext(int thread_num);
250
251 template <class T>
252 Fault read(Addr addr, T &data, unsigned flags);
253
254 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
255
254 template <class T>
255 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
256
256 template <class T>
257 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
258
259 Fault writeBytes(uint8_t *data, unsigned size,
260 Addr addr, unsigned flags, uint64_t *res);
261
257 void fetch();
258 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
259 void completeIfetch(PacketPtr );
260 void completeDataAccess(PacketPtr pkt);
261 void advanceInst(Fault fault);
262
263 /**
264 * Print state of address in memory system via PrintReq (for

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269 /**
270 * Finish a DTB translation.
271 * @param state The DTB translation state.
272 */
273 void finishTranslation(WholeTranslationState *state);
274
275 private:
276
262 void fetch();
263 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
264 void completeIfetch(PacketPtr );
265 void completeDataAccess(PacketPtr pkt);
266 void advanceInst(Fault fault);
267
268 /**
269 * Print state of address in memory system via PrintReq (for

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274 /**
275 * Finish a DTB translation.
276 * @param state The DTB translation state.
277 */
278 void finishTranslation(WholeTranslationState *state);
279
280 private:
281
282 // The backend for writeBytes and write. It's the same as writeBytes, but
283 // doesn't make a copy of data.
284 Fault writeTheseBytes(uint8_t *data, unsigned size,
285 Addr addr, unsigned flags, uint64_t *res);
286
277 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
278 FetchEvent fetchEvent;
279
280 struct IprEvent : Event {
281 Packet *pkt;
282 TimingSimpleCPU *cpu;
283 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
284 virtual void process();
285 virtual const char *description() const;
286 };
287
288 void completeDrain();
289};
290
291#endif // __CPU_SIMPLE_TIMING_HH__
287 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
288 FetchEvent fetchEvent;
289
290 struct IprEvent : Event {
291 Packet *pkt;
292 TimingSimpleCPU *cpu;
293 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
294 virtual void process();
295 virtual const char *description() const;
296 };
297
298 void completeDrain();
299};
300
301#endif // __CPU_SIMPLE_TIMING_HH__