timing.hh (6023:47b4fcb10c11) | timing.hh (6973:a123bd350935) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_SIMPLE_TIMING_HH__ 32#define __CPU_SIMPLE_TIMING_HH__ 33 34#include "cpu/simple/base.hh" | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_SIMPLE_TIMING_HH__ 32#define __CPU_SIMPLE_TIMING_HH__ 33 34#include "cpu/simple/base.hh" |
35#include "cpu/translation.hh" |
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35 36#include "params/TimingSimpleCPU.hh" 37 38class TimingSimpleCPU : public BaseSimpleCPU 39{ 40 public: 41 42 TimingSimpleCPU(TimingSimpleCPUParams * params); --- 67 unchanged lines hidden (view full) --- 110 finish(Fault fault, RequestPtr req, ThreadContext *tc, 111 BaseTLB::Mode mode) 112 { 113 cpu->sendFetch(fault, req, tc); 114 } 115 }; 116 FetchTranslation fetchTranslation; 117 | 36 37#include "params/TimingSimpleCPU.hh" 38 39class TimingSimpleCPU : public BaseSimpleCPU 40{ 41 public: 42 43 TimingSimpleCPU(TimingSimpleCPUParams * params); --- 67 unchanged lines hidden (view full) --- 111 finish(Fault fault, RequestPtr req, ThreadContext *tc, 112 BaseTLB::Mode mode) 113 { 114 cpu->sendFetch(fault, req, tc); 115 } 116 }; 117 FetchTranslation fetchTranslation; 118 |
118 class DataTranslation : public BaseTLB::Translation 119 { 120 protected: 121 TimingSimpleCPU *cpu; 122 uint8_t *data; 123 uint64_t *res; 124 BaseTLB::Mode mode; | 119 void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read); 120 void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req, 121 uint8_t *data, bool read); |
125 | 122 |
126 public: 127 DataTranslation(TimingSimpleCPU *_cpu, 128 uint8_t *_data, uint64_t *_res, BaseTLB::Mode _mode) 129 : cpu(_cpu), data(_data), res(_res), mode(_mode) 130 { 131 assert(mode == BaseTLB::Read || mode == BaseTLB::Write); 132 } 133 134 void 135 finish(Fault fault, RequestPtr req, ThreadContext *tc, 136 BaseTLB::Mode mode) 137 { 138 assert(mode == this->mode); 139 cpu->sendData(fault, req, data, res, mode == BaseTLB::Read); 140 delete this; 141 } 142 }; 143 144 class SplitDataTranslation : public BaseTLB::Translation 145 { 146 public: 147 struct WholeTranslationState 148 { 149 public: 150 int outstanding; 151 RequestPtr requests[2]; 152 RequestPtr mainReq; 153 Fault faults[2]; 154 uint8_t *data; 155 BaseTLB::Mode mode; 156 157 WholeTranslationState(RequestPtr req1, RequestPtr req2, 158 RequestPtr main, uint8_t *data, BaseTLB::Mode mode) 159 { 160 assert(mode == BaseTLB::Read || mode == BaseTLB::Write); 161 162 outstanding = 2; 163 requests[0] = req1; 164 requests[1] = req2; 165 mainReq = main; 166 faults[0] = faults[1] = NoFault; 167 this->data = data; 168 this->mode = mode; 169 } 170 }; 171 172 TimingSimpleCPU *cpu; 173 int index; 174 WholeTranslationState *state; 175 176 SplitDataTranslation(TimingSimpleCPU *_cpu, int _index, 177 WholeTranslationState *_state) 178 : cpu(_cpu), index(_index), state(_state) 179 {} 180 181 void 182 finish(Fault fault, RequestPtr req, ThreadContext *tc, 183 BaseTLB::Mode mode) 184 { 185 assert(state); 186 assert(state->outstanding); 187 state->faults[index] = fault; 188 if (--state->outstanding == 0) { 189 cpu->sendSplitData(state->faults[0], 190 state->faults[1], 191 state->requests[0], 192 state->requests[1], 193 state->mainReq, 194 state->data, 195 state->mode == BaseTLB::Read); 196 delete state; 197 } 198 delete this; 199 } 200 }; 201 202 void sendData(Fault fault, RequestPtr req, 203 uint8_t *data, uint64_t *res, bool read); 204 void sendSplitData(Fault fault1, Fault fault2, 205 RequestPtr req1, RequestPtr req2, RequestPtr req, 206 uint8_t *data, bool read); 207 | |
208 void translationFault(Fault fault); 209 210 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read); 211 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 212 RequestPtr req1, RequestPtr req2, RequestPtr req, 213 uint8_t *data, bool read); 214 215 bool handleReadPacket(PacketPtr pkt); --- 130 unchanged lines hidden (view full) --- 346 void advanceInst(Fault fault); 347 348 /** 349 * Print state of address in memory system via PrintReq (for 350 * debugging). 351 */ 352 void printAddr(Addr a); 353 | 123 void translationFault(Fault fault); 124 125 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read); 126 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 127 RequestPtr req1, RequestPtr req2, RequestPtr req, 128 uint8_t *data, bool read); 129 130 bool handleReadPacket(PacketPtr pkt); --- 130 unchanged lines hidden (view full) --- 261 void advanceInst(Fault fault); 262 263 /** 264 * Print state of address in memory system via PrintReq (for 265 * debugging). 266 */ 267 void printAddr(Addr a); 268 |
269 /** 270 * Finish a DTB translation. 271 * @param state The DTB translation state. 272 */ 273 void finishTranslation(WholeTranslationState *state); 274 |
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354 private: 355 356 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 357 FetchEvent fetchEvent; 358 359 struct IprEvent : Event { 360 Packet *pkt; 361 TimingSimpleCPU *cpu; 362 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 363 virtual void process(); 364 virtual const char *description() const; 365 }; 366 367 void completeDrain(); 368}; 369 370#endif // __CPU_SIMPLE_TIMING_HH__ | 275 private: 276 277 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 278 FetchEvent fetchEvent; 279 280 struct IprEvent : Event { 281 Packet *pkt; 282 TimingSimpleCPU *cpu; 283 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 284 virtual void process(); 285 virtual const char *description() const; 286 }; 287 288 void completeDrain(); 289}; 290 291#endif // __CPU_SIMPLE_TIMING_HH__ |