timing.hh (5890:bdef71accd68) timing.hh (5894:8091ac99341a)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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91 clearFromParent()
92 {
93 SplitMainSenderState * main_send_state =
94 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95 main_send_state->fragments[index] = NULL;
96 }
97 };
98
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 82 unchanged lines hidden (view full) ---

91 clearFromParent()
92 {
93 SplitMainSenderState * main_send_state =
94 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95 main_send_state->fragments[index] = NULL;
96 }
97 };
98
99 Fault buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, RequestPtr &req,
100 Addr split_addr, uint8_t *data, bool read);
101 Fault buildPacket(PacketPtr &pkt, RequestPtr &req, bool read);
99 class FetchTranslation : public BaseTLB::Translation
100 {
101 protected:
102 TimingSimpleCPU *cpu;
102
103
104 public:
105 FetchTranslation(TimingSimpleCPU *_cpu) : cpu(_cpu)
106 {}
107
108 void finish(Fault fault, RequestPtr req,
109 ThreadContext *tc, bool write)
110 {
111 cpu->sendFetch(fault, req, tc);
112 }
113 };
114 FetchTranslation fetchTranslation;
115
116 class DataTranslation : public BaseTLB::Translation
117 {
118 protected:
119 TimingSimpleCPU *cpu;
120 uint8_t *data;
121 uint64_t *res;
122 bool read;
123
124 public:
125 DataTranslation(TimingSimpleCPU *_cpu,
126 uint8_t *_data, uint64_t *_res, bool _read) :
127 cpu(_cpu), data(_data), res(_res), read(_read)
128 {}
129
130 void
131 finish(Fault fault, RequestPtr req,
132 ThreadContext *tc, bool write)
133 {
134 cpu->sendData(fault, req, data, res, read);
135 delete this;
136 }
137 };
138
139 class SplitDataTranslation : public BaseTLB::Translation
140 {
141 public:
142 struct WholeTranslationState
143 {
144 public:
145 int outstanding;
146 RequestPtr requests[2];
147 RequestPtr mainReq;
148 Fault faults[2];
149 uint8_t *data;
150 bool read;
151
152 WholeTranslationState(RequestPtr req1, RequestPtr req2,
153 RequestPtr main, uint8_t *_data, bool _read)
154 {
155 outstanding = 2;
156 requests[0] = req1;
157 requests[1] = req2;
158 mainReq = main;
159 faults[0] = faults[1] = NoFault;
160 data = _data;
161 read = _read;
162 }
163 };
164
165 TimingSimpleCPU *cpu;
166 int index;
167 WholeTranslationState *state;
168
169 SplitDataTranslation(TimingSimpleCPU *_cpu, int _index,
170 WholeTranslationState *_state) :
171 cpu(_cpu), index(_index), state(_state)
172 {}
173
174 void
175 finish(Fault fault, RequestPtr req,
176 ThreadContext *tc, bool write)
177 {
178 assert(state);
179 assert(state->outstanding);
180 state->faults[index] = fault;
181 if (--state->outstanding == 0) {
182 cpu->sendSplitData(state->faults[0],
183 state->faults[1],
184 state->requests[0],
185 state->requests[1],
186 state->mainReq,
187 state->data,
188 state->read);
189 delete state;
190 }
191 delete this;
192 }
193 };
194
195 void sendData(Fault fault, RequestPtr req,
196 uint8_t *data, uint64_t *res, bool read);
197 void sendSplitData(Fault fault1, Fault fault2,
198 RequestPtr req1, RequestPtr req2, RequestPtr req,
199 uint8_t *data, bool read);
200
201 void translationFault(Fault fault);
202
203 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
204 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
205 RequestPtr req1, RequestPtr req2, RequestPtr req,
206 uint8_t *data, bool read);
207
103 bool handleReadPacket(PacketPtr pkt);
104 // This function always implicitly uses dcache_pkt.
105 bool handleWritePacket();
106
107 class CpuPort : public Port
108 {
109 protected:
110 TimingSimpleCPU *cpu;

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223
224 template <class T>
225 Fault read(Addr addr, T &data, unsigned flags);
226
227 template <class T>
228 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
229
230 void fetch();
208 bool handleReadPacket(PacketPtr pkt);
209 // This function always implicitly uses dcache_pkt.
210 bool handleWritePacket();
211
212 class CpuPort : public Port
213 {
214 protected:
215 TimingSimpleCPU *cpu;

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328
329 template <class T>
330 Fault read(Addr addr, T &data, unsigned flags);
331
332 template <class T>
333 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
334
335 void fetch();
336 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
231 void completeIfetch(PacketPtr );
337 void completeIfetch(PacketPtr );
232 void completeDataAccess(PacketPtr );
338 void completeDataAccess(PacketPtr pkt);
233 void advanceInst(Fault fault);
234
235 /**
236 * Print state of address in memory system via PrintReq (for
237 * debugging).
238 */
239 void printAddr(Addr a);
240

--- 17 unchanged lines hidden --- 		339 void advanceInst(Fault fault);
340
341 /**
342 * Print state of address in memory system via PrintReq (for
343 * debugging).
344 */
345 void printAddr(Addr a);
346

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