timing.hh (5529:9ae69b9cd7fd) timing.hh (5606:6da7a58b0bc8)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 66 unchanged lines hidden (view full) ---

75 bool &snoop)
76 { resp.clear(); snoop = false; }
77
78 struct TickEvent : public Event
79 {
80 PacketPtr pkt;
81 TimingSimpleCPU *cpu;
82
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 66 unchanged lines hidden (view full) ---

75 bool &snoop)
76 { resp.clear(); snoop = false; }
77
78 struct TickEvent : public Event
79 {
80 PacketPtr pkt;
81 TimingSimpleCPU *cpu;
82
83 TickEvent(TimingSimpleCPU *_cpu)
84 :Event(&mainEventQueue), cpu(_cpu) {}
83 TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
85 const char *description() const { return "Timing CPU tick"; }
86 void schedule(PacketPtr _pkt, Tick t);
87 };
88
89 };
90
91 class IcachePort : public CpuPort
92 {

--- 117 unchanged lines hidden --- 		84 const char *description() const { return "Timing CPU tick"; }
85 void schedule(PacketPtr _pkt, Tick t);
86 };
87
88 };
89
90 class IcachePort : public CpuPort
91 {

--- 117 unchanged lines hidden ---