timing.hh (4475:fb185cc1c845) | timing.hh (4873:b135f6e6adfe) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 87 unchanged lines hidden (view full) --- 96 97 struct TickEvent : public Event 98 { 99 PacketPtr pkt; 100 TimingSimpleCPU *cpu; 101 102 TickEvent(TimingSimpleCPU *_cpu) 103 :Event(&mainEventQueue), cpu(_cpu) {} | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 87 unchanged lines hidden (view full) --- 96 97 struct TickEvent : public Event 98 { 99 PacketPtr pkt; 100 TimingSimpleCPU *cpu; 101 102 TickEvent(TimingSimpleCPU *_cpu) 103 :Event(&mainEventQueue), cpu(_cpu) {} |
104 const char *description() { return "Timing CPU clock event"; } | 104 const char *description() { return "Timing CPU tick"; } |
105 void schedule(PacketPtr _pkt, Tick t); 106 }; 107 108 }; 109 110 class IcachePort : public CpuPort 111 { 112 public: --- 9 unchanged lines hidden (view full) --- 122 virtual void recvRetry(); 123 124 struct ITickEvent : public TickEvent 125 { 126 127 ITickEvent(TimingSimpleCPU *_cpu) 128 : TickEvent(_cpu) {} 129 void process(); | 105 void schedule(PacketPtr _pkt, Tick t); 106 }; 107 108 }; 109 110 class IcachePort : public CpuPort 111 { 112 public: --- 9 unchanged lines hidden (view full) --- 122 virtual void recvRetry(); 123 124 struct ITickEvent : public TickEvent 125 { 126 127 ITickEvent(TimingSimpleCPU *_cpu) 128 : TickEvent(_cpu) {} 129 void process(); |
130 const char *description() { return "Timing CPU clock event"; } | 130 const char *description() { return "Timing CPU icache tick"; } |
131 }; 132 133 ITickEvent tickEvent; 134 135 }; 136 137 class DcachePort : public CpuPort 138 { --- 11 unchanged lines hidden (view full) --- 150 151 virtual void recvRetry(); 152 153 struct DTickEvent : public TickEvent 154 { 155 DTickEvent(TimingSimpleCPU *_cpu) 156 : TickEvent(_cpu) {} 157 void process(); | 131 }; 132 133 ITickEvent tickEvent; 134 135 }; 136 137 class DcachePort : public CpuPort 138 { --- 11 unchanged lines hidden (view full) --- 150 151 virtual void recvRetry(); 152 153 struct DTickEvent : public TickEvent 154 { 155 DTickEvent(TimingSimpleCPU *_cpu) 156 : TickEvent(_cpu) {} 157 void process(); |
158 const char *description() { return "Timing CPU clock event"; } | 158 const char *description() { return "Timing CPU dcache tick"; } |
159 }; 160 161 DTickEvent tickEvent; 162 163 }; 164 165 IcachePort icachePort; 166 DcachePort dcachePort; --- 43 unchanged lines hidden --- | 159 }; 160 161 DTickEvent tickEvent; 162 163 }; 164 165 IcachePort icachePort; 166 DcachePort dcachePort; --- 43 unchanged lines hidden --- |